f183444682
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
77 lines
4.1 KiB
Text
77 lines
4.1 KiB
Text
/* SoC level DTS fixup file */
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#define CONFIG_UART_QMSI_0_BAUDRATE INTEL_QMSI_UART_B0002000_CURRENT_SPEED
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#define CONFIG_UART_QMSI_0_NAME INTEL_QMSI_UART_B0002000_LABEL
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#define CONFIG_UART_QMSI_0_IRQ INTEL_QMSI_UART_B0002000_IRQ_0
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#define CONFIG_UART_QMSI_0_IRQ_PRI INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY
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#define CONFIG_UART_QMSI_1_BAUDRATE INTEL_QMSI_UART_B0002400_CURRENT_SPEED
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#define CONFIG_UART_QMSI_1_NAME INTEL_QMSI_UART_B0002400_LABEL
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#define CONFIG_UART_QMSI_1_IRQ INTEL_QMSI_UART_B0002400_IRQ_0
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#define CONFIG_UART_QMSI_1_IRQ_PRI INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY
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#define SRAM_START CONFIG_SRAM_BASE_ADDRESS
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#define SRAM_SIZE CONFIG_SRAM_SIZE
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#define FLASH_START CONFIG_FLASH_BASE_ADDRESS
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS
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#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10)
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#define CONFIG_I2C_SS_0_NAME INTEL_QMSI_SS_I2C_80012000_LABEL
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#define CONFIG_I2C_SS_0_ERR_IRQ INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR
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#define CONFIG_I2C_SS_0_ERR_IRQ_PRI INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY
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#define CONFIG_I2C_SS_0_RX_IRQ INTEL_QMSI_SS_I2C_80012000_IRQ_RX
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#define CONFIG_I2C_SS_0_RX_IRQ_PRI INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY
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#define CONFIG_I2C_SS_0_TX_IRQ INTEL_QMSI_SS_I2C_80012000_IRQ_TX
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#define CONFIG_I2C_SS_0_TX_IRQ_PRI INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY
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#define CONFIG_I2C_SS_0_STOP_IRQ INTEL_QMSI_SS_I2C_80012000_IRQ_STOP
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#define CONFIG_I2C_SS_0_STOP_IRQ_PRI INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY
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#define CONFIG_I2C_SS_0_BITRATE INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY
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#define CONFIG_I2C_SS_1_NAME INTEL_QMSI_SS_I2C_80012100_LABEL
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#define CONFIG_I2C_SS_1_ERR_IRQ INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR
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#define CONFIG_I2C_SS_1_ERR_IRQ_PRI INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY
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#define CONFIG_I2C_SS_1_RX_IRQ INTEL_QMSI_SS_I2C_80012100_IRQ_RX
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#define CONFIG_I2C_SS_1_RX_IRQ_PRI INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY
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#define CONFIG_I2C_SS_1_TX_IRQ INTEL_QMSI_SS_I2C_80012100_IRQ_TX
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#define CONFIG_I2C_SS_1_TX_IRQ_PRI INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY
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#define CONFIG_I2C_SS_1_STOP_IRQ INTEL_QMSI_SS_I2C_80012100_IRQ_STOP
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#define CONFIG_I2C_SS_1_STOP_IRQ_PRI INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY
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#define CONFIG_I2C_SS_1_BITRATE INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_NAME INTEL_QMSI_I2C_B0002800_LABEL
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#define CONFIG_I2C_0_BITRATE INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_IRQ INTEL_QMSI_I2C_B0002800_IRQ_0
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#define CONFIG_I2C_0_IRQ_PRI INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY
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#define CONFIG_I2C_1_NAME INTEL_QMSI_I2C_B0002C00_LABEL
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#define CONFIG_I2C_1_BITRATE INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY
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#define CONFIG_I2C_1_IRQ INTEL_QMSI_I2C_B0002C00_IRQ_0
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#define CONFIG_I2C_1_IRQ_PRI INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY
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#define CONFIG_RTC_0_NAME INTEL_QMSI_RTC_B0000400_LABEL
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#define CONFIG_RTC_0_IRQ INTEL_QMSI_RTC_B0000400_IRQ_0
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#define CONFIG_RTC_0_IRQ_PRI INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY
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#define CONFIG_GPIO_QMSI_SS_0_NAME INTEL_QMSI_SS_GPIO_80017800_LABEL
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#define CONFIG_GPIO_QMSI_SS_0_IRQ INTEL_QMSI_SS_GPIO_80017800_IRQ_0
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#define CONFIG_GPIO_QMSI_SS_0_IRQ_PRI INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY
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#define CONFIG_GPIO_QMSI_SS_1_NAME INTEL_QMSI_SS_GPIO_80017900_LABEL
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#define CONFIG_GPIO_QMSI_SS_1_IRQ INTEL_QMSI_SS_GPIO_80017900_IRQ_0
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#define CONFIG_GPIO_QMSI_SS_1_IRQ_PRI INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY
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#define CONFIG_GPIO_QMSI_0_NAME INTEL_QMSI_GPIO_B0000C00_LABEL
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#define CONFIG_GPIO_QMSI_0_IRQ INTEL_QMSI_GPIO_B0000C00_IRQ_0
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#define CONFIG_GPIO_QMSI_0_IRQ_PRI INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY
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#define CONFIG_GPIO_QMSI_1_NAME INTEL_QMSI_GPIO_B0800B00_LABEL
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#define CONFIG_GPIO_QMSI_1_IRQ INTEL_QMSI_GPIO_B0800B00_IRQ_0
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#define CONFIG_GPIO_QMSI_1_IRQ_PRI INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY
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#define CONFIG_ADC_0_IRQ SNPS_DW_ADC_80015000_IRQ_NORMAL
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#define CONFIG_ADC_IRQ_ERR SNPS_DW_ADC_80015000_IRQ_ERROR
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#define CONFIG_ADC_0_IRQ_PRI SNPS_DW_ADC_80015000_IRQ_0_PRIORITY
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#define CONFIG_ADC_0_NAME SNPS_DW_ADC_80015000_LABEL
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#define CONFIG_ADC_0_BASE_ADDRESS SNPS_DW_ADC_80015000_BASE_ADDRESS
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/* End of SoC Level DTS fixup file */
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