efc2cfe326
Per the docs, the memory at address 0x80000000 ends at 0xC0000000. In other words, the address space is 0x40000000, which is only half of the size we want to map. This means that the upper address space previously mapped was overlapping with the space reserved for non-cached memory. Instead, we map the entire 2GB at 0x1000000000, which is the correct address for cached DDR that occupies more than 1 GB. We defined a new node in the device tree for this memory region, `beaglev.ddr_cached_high`. We did not reuse the `soc` node because we needed to redefine the `#address-cells` to be 2, and doing so would have affected other nodes under `soc`. Signed-off-by: Alex Charlton <alex.n.charlton@gmail.com>
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.. zephyr:board:: beaglev_fire
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Overview
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********
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BeagleV®-Fire is a revolutionary single-board computer (SBC) powered by the Microchip’s
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PolarFire® MPFS025T 5x core RISC-V System on Chip (SoC) with FPGA fabric. BeagleV®-Fire opens up new
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horizons for developers, tinkerers, and the open-source community to explore the vast potential of
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RISC-V architecture and FPGA technology. It has the same P8 & P9 cape header pins as BeagleBone
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Black allowing you to stack your favorite BeagleBone cape on top to expand it’s capability.
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Built around the powerful and energy-efficient RISC-V instruction set architecture (ISA) along with
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its versatile FPGA fabric, BeagleV®-Fire SBC offers unparalleled opportunities for developers,
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hobbyists, and researchers to explore and experiment with RISC-V technology.
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Building
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========
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There are three board configurations provided for the BeagleV-Fire:
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* ``beaglev_fire/polarfire/e51``: Uses only the E51 core
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* ``beaglev_fire/polarfire/u54``: Uses the U54 cores
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* ``beaglev_fire/polarfire/u54/smp``: Uses the U54 cores with CONFIG_SMP=y
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Applications for the ``beaglev_fire`` board configuration can be built as usual:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: beaglev_fire/polarfire/u54
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:goals: build
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Debugging
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=========
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In order to upload the application to the device, you'll need OpenOCD and GDB
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with RISC-V support.
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You can get them as a part of SoftConsole SDK.
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Download and installation instructions can be found on
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`Microchip's SoftConsole website
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<https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/programming-and-debug/softconsole>`_.
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You will also require a Debugger such as Microchip's FlashPro5/6.
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Connect to BeagleV-Fire UART debug port using a 3.3v USB to UART bridge.
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Now you can run ``tio <port>`` in a terminal window to access the UART debug port connection. Once you
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are connected properly you can press the Reset button which will show you a progress bar like:
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.. image:: img/board-booting.png
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:align: center
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:alt: beaglev_fire
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Once you see that progress bar on your screen you can start pressing any button (0-9/a-z) which
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will interrupt the Hart Software Services from booting its payload.
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With the necessary tools installed, you can connect to the board using OpenOCD.
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from a different terminal, run:
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.. code-block:: bash
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<softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
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<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
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Leave it running, and in a different terminal, use GDB to upload the binary to
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the board. You can use the RISC-V GDB from the Zephyr SDK.
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launch GDB:
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.. code-block:: bash
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<path_to_zephyr_sdk>/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gdb
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Here is the GDB terminal command to connect to the device
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and load the binary:
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.. code-block:: bash
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set arch riscv:rv64
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set mem inaccessible-by-default off
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file <path_to_zehyr.elf>
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target extended-remote localhost:3333
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load
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break main
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continue
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Flashing
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========
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When using the PolarFire `Hart Software Services <https://github.com/polarfire-soc/hart-software-services>`_ along with Zephyr, you need to use the `hss-payload-generator <https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator>`_ tool to generate an image that HSS can boot.
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.. code-block:: yaml
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set-name: 'ZephyrImage'
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# Define the entry point address for each hart (U54 cores)
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hart-entry-points:
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u54_1: '0x1000000000'
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# Define the payloads (ELF binaries or raw blobs)
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payloads:
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<path_to_zephyr.elf>:
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exec-addr: '0x1000000000' # Where Zephyr should be loaded
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owner-hart: u54_1 # Primary hart that runs Zephyr
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priv-mode: prv_m # Start in Machine mode
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skip-opensbi: true # Boot directly without OpenSBI
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After generating the image, you can flash it to the board by restarting a board that's connected over USB and UART, interrupting the HSS boot process with a key press, and then running the ``mmc`` and ``usbdmsc`` commands:
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.. code-block:: bash
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Press a key to enter CLI, ESC to skip
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Timeout in 1 second
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.[6.304162] Character 100 pressed
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[6.308415] Type HELP for list of commands
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[6.313276] >> mmc
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[10.450867] Selecting SDCARD/MMC (fallback) as boot source ...
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[10.457550] Attempting to select eMMC ... Passed
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[10.712708] >> usbdmsc
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[14.732841] initialize MMC
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[14.736400] Attempting to select eMMC ... Passed
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[15.168707] MMC - 512 byte pages, 512 byte blocks, 30621696 pages
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Waiting for USB Host to connect... (CTRL-C to quit)
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. 0 bytes written, 0 bytes read
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USB Host connected. Waiting for disconnect... (CTRL-C to quit)
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/ 0 bytes written, 219136 bytes read
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This will cause the board to appear as a USB mass storage device. You can then then flash the image with ``dd`` or other tools like `BalenaEtcher <https://www.balena.io/etcher/>`_:
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.. code-block:: bash
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dd if=<path_to_zephyr.elf> of=/dev/sdXD bs=4M status=progress oflag=sync
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