ef4cd76970
Add a new timeout_s parameter that can also be 'None' = infinite. No functional change. Required to add future support for DSP power state: D3 Signed-off-by: Marc Herbert <marc.herbert@intel.com>
898 lines
32 KiB
Python
Executable file
898 lines
32 KiB
Python
Executable file
#!/usr/bin/env python3
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# Copyright(c) 2022 Intel Corporation. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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import os
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import sys
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import struct
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import logging
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import asyncio
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import time
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import subprocess
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import ctypes
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import mmap
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import argparse
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import socketserver
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import threading
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import netifaces
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import hashlib
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# Global variable use to sync between log and request services.
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# When it is true, the adsp is able to start running.
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start_output = False
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lock = threading.Lock()
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HOST = None
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PORT_LOG = 9999
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PORT_REQ = PORT_LOG + 1
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BUF_SIZE = 4096
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# Define the command and the max size
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CMD_LOG_START = "start_log"
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CMD_DOWNLOAD = "download"
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MAX_CMD_SZ = 16
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# Define the header format and size for
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# transmiting the firmware
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PACKET_HEADER_FORMAT_FW = 'I 42s 32s'
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HEADER_SZ = 78
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logging.basicConfig()
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log = logging.getLogger("cavs-fw")
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log.setLevel(logging.INFO)
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PAGESZ = 4096
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HUGEPAGESZ = 2 * 1024 * 1024
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HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp."
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# SRAM windows. Each appears in a 128k region starting at 512k.
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#
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# Window 0 is the FW_STATUS area, and 4k after that the IPC "outbox"
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# Window 1 is the IPC "inbox" (host-writable memory, just 384 bytes currently)
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# Window 2 is unused by this script
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# Window 3 is winstream-formatted log output
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OUTBOX_OFFSET = (512 + (0 * 128)) * 1024 + 4096
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INBOX_OFFSET = (512 + (1 * 128)) * 1024
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WINSTREAM_OFFSET = (512 + (3 * 128)) * 1024
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# ADSPCS bits
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CRST = 0
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CSTALL = 8
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SPA = 16
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CPA = 24
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class HDAStream:
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# creates an hda stream with at 2 buffers of buf_len
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def __init__(self, stream_id: int):
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self.stream_id = stream_id
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self.base = hdamem + 0x0080 + (stream_id * 0x20)
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log.info(f"Mapping registers for hda stream {self.stream_id} at base {self.base:x}")
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self.hda = Regs(hdamem)
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self.hda.GCAP = 0x0000
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self.hda.GCTL = 0x0008
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self.hda.DPLBASE = 0x0070
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self.hda.DPUBASE = 0x0074
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self.hda.SPBFCH = 0x0700
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self.hda.SPBFCTL = 0x0704
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self.hda.PPCH = 0x0800
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self.hda.PPCTL = 0x0804
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self.hda.PPSTS = 0x0808
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self.hda.SPIB = 0x0708 + stream_id*0x08
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self.hda.freeze()
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self.regs = Regs(self.base)
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self.regs.CTL = 0x00
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self.regs.STS = 0x03
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self.regs.LPIB = 0x04
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self.regs.CBL = 0x08
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self.regs.LVI = 0x0c
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self.regs.FIFOW = 0x0e
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self.regs.FIFOS = 0x10
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self.regs.FMT = 0x12
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self.regs.FIFOL= 0x14
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self.regs.BDPL = 0x18
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self.regs.BDPU = 0x1c
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self.regs.freeze()
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self.dbg0 = Regs(hdamem + 0x0084 + (0x20*stream_id))
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self.dbg0.DPIB = 0x00
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self.dbg0.EFIFOS = 0x10
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self.dbg0.freeze()
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self.reset()
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def __del__(self):
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self.reset()
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def config(self, buf_len: int):
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log.info(f"Configuring stream {self.stream_id}")
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self.buf_len = buf_len
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log.info("Allocating huge page and setting up buffers")
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self.mem, self.hugef, self.buf_list_addr, self.pos_buf_addr, self.n_bufs = self.setup_buf(buf_len)
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log.info("Setting buffer list, length, and stream id and traffic priority bit")
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self.regs.CTL = ((self.stream_id & 0xFF) << 20) | (1 << 18) # must be set to something other than 0?
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self.regs.BDPU = (self.buf_list_addr >> 32) & 0xffffffff
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self.regs.BDPL = self.buf_list_addr & 0xffffffff
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self.regs.CBL = buf_len
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self.regs.LVI = self.n_bufs - 1
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self.debug()
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log.info(f"Configured stream {self.stream_id}")
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def write(self, data):
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bufl = min(len(data), self.buf_len)
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log.info(f"Writing data to stream {self.stream_id}, len {bufl}, SPBFCTL {self.hda.SPBFCTL:x}, SPIB {self.hda.SPIB}")
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self.mem[0:bufl] = data[0:bufl]
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self.mem[bufl:bufl+bufl] = data[0:bufl]
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self.hda.SPBFCTL |= (1 << self.stream_id)
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self.hda.SPIB += bufl
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log.info(f"Wrote data to stream {self.stream_id}, SPBFCTL {self.hda.SPBFCTL:x}, SPIB {self.hda.SPIB}")
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def start(self):
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log.info(f"Starting stream {self.stream_id}, CTL {self.regs.CTL:x}")
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self.regs.CTL |= 2
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log.info(f"Started stream {self.stream_id}, CTL {self.regs.CTL:x}")
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def stop(self):
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log.info(f"Stopping stream {self.stream_id}, CTL {self.regs.CTL:x}")
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self.regs.CTL &= 2
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time.sleep(0.1)
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self.regs.CTL |= 1
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log.info(f"Stopped stream {self.stream_id}, CTL {self.regs.CTL:x}")
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def setup_buf(self, buf_len: int):
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(mem, phys_addr, hugef) = map_phys_mem(self.stream_id)
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log.info(f"Mapped 2M huge page at 0x{phys_addr:x} for buf size ({buf_len})")
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# create two buffers in the page of buf_len and mark them
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# in a buffer descriptor list for the hardware to use
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buf0_len = buf_len
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buf1_len = buf_len
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bdl_off = buf0_len + buf1_len
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# bdl is 2 (64bits, 16 bytes) per entry, we have two
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mem[bdl_off:bdl_off + 32] = struct.pack("<QQQQ",
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phys_addr,
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buf0_len,
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phys_addr + buf0_len,
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buf1_len)
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dpib_off = bdl_off+32
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# ensure buffer is initialized, sanity
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for i in range(0, buf_len*2):
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mem[i] = 0
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log.info("Filled the buffer descriptor list (BDL) for DMA.")
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return (mem, hugef, phys_addr + bdl_off, phys_addr+dpib_off, 2)
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def debug(self):
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log.info("HDA %d: PPROC %d, CTL 0x%x, LPIB 0x%x, BDPU 0x%x, BDPL 0x%x, CBL 0x%x, LVI 0x%x",
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self.stream_id, (hda.PPCTL >> self.stream_id) & 1, self.regs.CTL, self.regs.LPIB, self.regs.BDPU,
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self.regs.BDPL, self.regs.CBL, self.regs.LVI)
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log.info(" FIFOW %d, FIFOS %d, FMT %x, FIFOL %d, DPIB %d, EFIFOS %d",
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self.regs.FIFOW & 0x7, self.regs.FIFOS, self.regs.FMT, self.regs.FIFOL, self.dbg0.DPIB, self.dbg0.EFIFOS)
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log.info(" status: FIFORDY %d, DESE %d, FIFOE %d, BCIS %d",
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(self.regs.STS >> 5) & 1, (self.regs.STS >> 4) & 1, (self.regs.STS >> 3) & 1, (self.regs.STS >> 2) & 1)
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def reset(self):
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# Turn DMA off and reset the stream. Clearing START first is a
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# noop per the spec, but absolutely required for stability.
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# Apparently the reset doesn't stop the stream, and the next load
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# starts before it's ready and kills the load (and often the DSP).
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# The sleep too is required, on at least one board (a fast
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# chromebook) putting the two writes next each other also hangs
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# the DSP!
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log.info(f"Resetting stream {self.stream_id}")
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self.debug()
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self.regs.CTL &= ~2 # clear START
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time.sleep(0.1)
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# set enter reset bit
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self.regs.CTL = 1
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while (self.regs.CTL & 1) == 0: pass
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# clear enter reset bit to exit reset
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self.regs.CTL = 0
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while (self.regs.CTL & 1) == 1: pass
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log.info(f"Disable SPIB and set position 0 of stream {self.stream_id}")
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self.hda.SPBFCTL = 0
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self.hda.SPIB = 0
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#log.info("Setting dma position buffer and enable it")
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#self.hda.DPUBASE = self.pos_buf_addr >> 32 & 0xffffffff
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#self.hda.DPLBASE = self.pos_buf_addr & 0xfffffff0 | 1
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log.info(f"Enabling dsp capture (PROCEN) of stream {self.stream_id}")
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self.hda.PPCTL |= (1 << self.stream_id)
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self.debug()
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log.info(f"Reset stream {self.stream_id}")
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def map_regs():
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p = runx(f"grep -iEl 'PCI_CLASS=40(10|38)0' /sys/bus/pci/devices/*/uevent")
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pcidir = os.path.dirname(p)
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# Platform/quirk detection. ID lists cribbed from the SOF kernel driver
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global cavs15, cavs18, cavs25
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did = int(open(f"{pcidir}/device").read().rstrip(), 16)
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cavs15 = did in [ 0x5a98, 0x1a98, 0x3198 ]
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cavs18 = did in [ 0x9dc8, 0xa348, 0x02c8, 0x06c8, 0xa3f0 ]
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cavs25 = did in [ 0xa0c8, 0x43c8, 0x4b55, 0x4b58, 0x7ad0, 0x51c8 ]
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# Check sysfs for a loaded driver and remove it
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if os.path.exists(f"{pcidir}/driver"):
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mod = os.path.basename(os.readlink(f"{pcidir}/driver/module"))
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found_msg = f"Existing driver \"{mod}\" found"
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if args.log_only:
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log.info(found_msg)
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else:
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log.warning(found_msg + ", unloading module")
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runx(f"rmmod -f {mod}")
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# Disengage runtime power management so the kernel doesn't put it to sleep
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with open(f"{pcidir}/power/control", "w") as ctrl:
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ctrl.write("on")
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# Make sure PCI memory space access and busmastering are enabled.
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# Also disable interrupts so as not to confuse the kernel.
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with open(f"{pcidir}/config", "wb+") as cfg:
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cfg.seek(4)
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cfg.write(b'\x06\x04')
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# Standard HD Audio Registers
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global hdamem
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(hdamem, _) = bar_map(pcidir, 0)
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hda = Regs(hdamem)
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hda.GCAP = 0x0000
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hda.GCTL = 0x0008
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hda.SPBFCTL = 0x0704
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hda.PPCTL = 0x0804
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# Find the ID of the first output stream
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hda_ostream_id = (hda.GCAP >> 8) & 0x0f # number of input streams
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log.info(f"Selected output stream {hda_ostream_id} (GCAP = 0x{hda.GCAP:x})")
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hda.SD_SPIB = 0x0708 + (8 * hda_ostream_id)
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hda.freeze()
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# Standard HD Audio Stream Descriptor
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sd = Regs(hdamem + 0x0080 + (hda_ostream_id * 0x20))
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sd.CTL = 0x00
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sd.CBL = 0x08
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sd.LVI = 0x0c
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sd.BDPL = 0x18
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sd.BDPU = 0x1c
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sd.freeze()
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# Intel Audio DSP Registers
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global bar4_mmap
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(bar4_mem, bar4_mmap) = bar_map(pcidir, 4)
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dsp = Regs(bar4_mem)
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dsp.ADSPCS = 0x00004
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dsp.HIPCTDR = 0x00040 if cavs15 else 0x000c0
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dsp.HIPCTDA = 0x000c4 # 1.8+ only
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dsp.HIPCTDD = 0x00044 if cavs15 else 0x000c8
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dsp.HIPCIDR = 0x00048 if cavs15 else 0x000d0
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dsp.HIPCIDA = 0x000d4 # 1.8+ only
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dsp.HIPCIDD = 0x0004c if cavs15 else 0x000d8
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dsp.SRAM_FW_STATUS = 0x80000 # Start of first SRAM window
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dsp.freeze()
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return (hda, sd, dsp, hda_ostream_id)
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def setup_dma_mem(fw_bytes):
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(mem, phys_addr, _) = map_phys_mem(hda_ostream_id)
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mem[0:len(fw_bytes)] = fw_bytes
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log.info("Mapped 2M huge page at 0x%x to contain %d bytes of firmware"
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% (phys_addr, len(fw_bytes)))
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# HDA requires at least two buffers be defined, but we don't care about
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# boundaries because it's all a contiguous region. Place a vestigial
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# 128-byte (minimum size and alignment) buffer after the main one, and put
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# the 4-entry BDL list into the final 128 bytes of the page.
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buf0_len = HUGEPAGESZ - 2 * 128
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buf1_len = 128
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bdl_off = buf0_len + buf1_len
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mem[bdl_off:bdl_off + 32] = struct.pack("<QQQQ",
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phys_addr, buf0_len,
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phys_addr + buf0_len, buf1_len)
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log.info("Filled the buffer descriptor list (BDL) for DMA.")
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return (phys_addr + bdl_off, 2)
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global_mmaps = [] # protect mmap mappings from garbage collection!
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# Maps 2M of contiguous memory using a single page from hugetlbfs,
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# then locates its physical address for use as a DMA buffer.
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def map_phys_mem(stream_id):
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# Make sure hugetlbfs is mounted (not there on chromeos)
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os.system("mount | grep -q hugetlbfs ||"
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+ " (mkdir -p /dev/hugepages; "
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+ " mount -t hugetlbfs hugetlbfs /dev/hugepages)")
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# Ensure the kernel has enough budget for one new page
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free = int(runx("awk '/HugePages_Free/ {print $2}' /proc/meminfo"))
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if free == 0:
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tot = 1 + int(runx("awk '/HugePages_Total/ {print $2}' /proc/meminfo"))
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os.system(f"echo {tot} > /proc/sys/vm/nr_hugepages")
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hugef_name = HUGEPAGE_FILE + str(stream_id)
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hugef = open(hugef_name, "w+")
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hugef.truncate(HUGEPAGESZ)
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mem = mmap.mmap(hugef.fileno(), HUGEPAGESZ)
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log.info("type of mem is %s", str(type(mem)))
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global_mmaps.append(mem)
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os.unlink(hugef_name)
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# Find the local process address of the mapping, then use that to extract
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# the physical address from the kernel's pagemap interface. The physical
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# page frame number occupies the bottom bits of the entry.
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mem[0] = 0 # Fault the page in so it has an address!
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vaddr = ctypes.addressof(ctypes.c_int.from_buffer(mem))
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vpagenum = vaddr >> 12
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pagemap = open("/proc/self/pagemap", "rb")
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pagemap.seek(vpagenum * 8)
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pent = pagemap.read(8)
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paddr = (struct.unpack("Q", pent)[0] & ((1 << 55) - 1)) * PAGESZ
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pagemap.close()
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return (mem, paddr, hugef)
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# Maps a PCI BAR and returns the in-process address
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def bar_map(pcidir, barnum):
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f = open(pcidir + "/resource" + str(barnum), "r+")
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mm = mmap.mmap(f.fileno(), os.fstat(f.fileno()).st_size)
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global_mmaps.append(mm)
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log.info("Mapped PCI bar %d of length %d bytes."
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% (barnum, os.fstat(f.fileno()).st_size))
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return (ctypes.addressof(ctypes.c_int.from_buffer(mm)), mm)
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# Syntactic sugar to make register block definition & use look nice.
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# Instantiate from a base address, assign offsets to (uint32) named registers as
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# fields, call freeze(), then the field acts as a direct alias for the register!
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class Regs:
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def __init__(self, base_addr):
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vars(self)["base_addr"] = base_addr
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vars(self)["ptrs"] = {}
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vars(self)["frozen"] = False
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def freeze(self):
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vars(self)["frozen"] = True
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def __setattr__(self, name, val):
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if not self.frozen and name not in self.ptrs:
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addr = self.base_addr + val
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self.ptrs[name] = ctypes.c_uint32.from_address(addr)
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else:
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self.ptrs[name].value = val
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def __getattr__(self, name):
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return self.ptrs[name].value
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def runx(cmd):
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return subprocess.check_output(cmd, shell=True).decode().rstrip()
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def mask(bit):
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if cavs25:
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return 0b1 << bit
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if cavs18:
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return 0b1111 << bit
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if cavs15:
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return 0b11 << bit
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def load_firmware(fw_file):
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try:
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fw_bytes = open(fw_file, "rb").read()
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except Exception as e:
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log.error(f"Could not read firmware file: `{fw_file}'")
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log.error(e)
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sys.exit(1)
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(magic, sz) = struct.unpack("4sI", fw_bytes[0:8])
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if magic == b'XMan':
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log.info(f"Trimming {sz} bytes of extended manifest")
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fw_bytes = fw_bytes[sz:len(fw_bytes)]
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# This actually means "enable access to BAR4 registers"!
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hda.PPCTL |= (1 << 30) # GPROCEN, "global processing enable"
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log.info("Resetting HDA device")
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hda.GCTL = 0
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while hda.GCTL & 1: pass
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hda.GCTL = 1
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while not hda.GCTL & 1: pass
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log.info(f"Stalling and Resetting DSP cores, ADSPCS = 0x{dsp.ADSPCS:x}")
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dsp.ADSPCS |= mask(CSTALL)
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dsp.ADSPCS |= mask(CRST)
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while (dsp.ADSPCS & mask(CRST)) == 0: pass
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log.info(f"Powering down DSP cores, ADSPCS = 0x{dsp.ADSPCS:x}")
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dsp.ADSPCS &= ~mask(SPA)
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while dsp.ADSPCS & mask(CPA): pass
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log.info(f"Configuring HDA stream {hda_ostream_id} to transfer firmware image")
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(buf_list_addr, num_bufs) = setup_dma_mem(fw_bytes)
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sd.CTL = 1
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while (sd.CTL & 1) == 0: pass
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sd.CTL = 0
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while (sd.CTL & 1) == 1: pass
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sd.CTL = (1 << 20) # Set stream ID to anything non-zero
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sd.BDPU = (buf_list_addr >> 32) & 0xffffffff
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sd.BDPL = buf_list_addr & 0xffffffff
|
|
sd.CBL = len(fw_bytes)
|
|
sd.LVI = num_bufs - 1
|
|
hda.PPCTL |= (1 << hda_ostream_id)
|
|
|
|
# SPIB ("Software Position In Buffer") is an Intel HDA extension
|
|
# that puts a transfer boundary into the stream beyond which the
|
|
# other side will not read. The ROM wants to poll on a "buffer
|
|
# full" bit on the other side that only works with this enabled.
|
|
hda.SPBFCTL |= (1 << hda_ostream_id)
|
|
hda.SD_SPIB = len(fw_bytes)
|
|
|
|
# Start DSP. Host needs to provide power to all cores on 1.5
|
|
# (which also starts them) and 1.8 (merely gates power, DSP also
|
|
# has to set PWRCTL). On 2.5 where the DSP has full control,
|
|
# and only core 0 is set.
|
|
log.info(f"Starting DSP, ADSPCS = 0x{dsp.ADSPCS:x}")
|
|
dsp.ADSPCS = mask(SPA)
|
|
while (dsp.ADSPCS & mask(CPA)) == 0: pass
|
|
|
|
log.info(f"Unresetting DSP cores, ADSPCS = 0x{dsp.ADSPCS:x}")
|
|
dsp.ADSPCS &= ~mask(CRST)
|
|
while (dsp.ADSPCS & 1) != 0: pass
|
|
|
|
log.info(f"Running DSP cores, ADSPCS = 0x{dsp.ADSPCS:x}")
|
|
dsp.ADSPCS &= ~mask(CSTALL)
|
|
|
|
# Wait for the ROM to boot and signal it's ready. This not so short
|
|
# sleep seems to be needed; if we're banging on the memory window
|
|
# during initial boot (before/while the window control registers
|
|
# are configured?) the DSP hardware will hang fairly reliably.
|
|
log.info(f"Wait for ROM startup, ADSPCS = 0x{dsp.ADSPCS:x}")
|
|
time.sleep(1)
|
|
while (dsp.SRAM_FW_STATUS >> 24) != 5: pass
|
|
|
|
# Send the DSP an IPC message to tell the device how to boot.
|
|
# Note: with cAVS 1.8+ the ROM receives the stream argument as an
|
|
# index within the array of output streams (and we always use the
|
|
# first one by construction). But with 1.5 it's the HDA index,
|
|
# and depends on the number of input streams on the device.
|
|
stream_idx = hda_ostream_id if cavs15 else 0
|
|
ipcval = ( (1 << 31) # BUSY bit
|
|
| (0x01 << 24) # type = PURGE_FW
|
|
| (1 << 14) # purge_fw = 1
|
|
| (stream_idx << 9)) # dma_id
|
|
log.info(f"Sending IPC command, HIPIDR = 0x{ipcval:x}")
|
|
dsp.HIPCIDR = ipcval
|
|
|
|
log.info(f"Starting DMA, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
|
|
sd.CTL |= 2 # START flag
|
|
|
|
wait_fw_entered()
|
|
|
|
# Turn DMA off and reset the stream. Clearing START first is a
|
|
# noop per the spec, but absolutely required for stability.
|
|
# Apparently the reset doesn't stop the stream, and the next load
|
|
# starts before it's ready and kills the load (and often the DSP).
|
|
# The sleep too is required, on at least one board (a fast
|
|
# chromebook) putting the two writes next each other also hangs
|
|
# the DSP!
|
|
sd.CTL &= ~2 # clear START
|
|
time.sleep(0.1)
|
|
sd.CTL |= 1
|
|
log.info(f"cAVS firmware load complete")
|
|
|
|
def fw_is_alive():
|
|
return dsp.SRAM_FW_STATUS & ((1 << 28) - 1) == 5 # "FW_ENTERED"
|
|
|
|
def wait_fw_entered(timeout_s=2):
|
|
log.info("Waiting %s for firmware handoff, FW_STATUS = 0x%x",
|
|
"forever" if timeout_s is None else f"{timeout_s} seconds",
|
|
dsp.SRAM_FW_STATUS)
|
|
hertz = 100
|
|
attempts = None if timeout_s is None else timeout_s * hertz
|
|
while True:
|
|
alive = fw_is_alive()
|
|
if alive:
|
|
break
|
|
if attempts is not None:
|
|
attempts -= 1
|
|
if attempts < 0:
|
|
break
|
|
time.sleep(1 / hertz)
|
|
|
|
if not alive:
|
|
log.warning("Load failed? FW_STATUS = 0x%x", dsp.SRAM_FW_STATUS)
|
|
else:
|
|
log.info("FW alive, FW_STATUS = 0x%x", dsp.SRAM_FW_STATUS)
|
|
|
|
|
|
# This SHOULD be just "mem[start:start+length]", but slicing an mmap
|
|
# array seems to be unreliable on one of my machines (python 3.6.9 on
|
|
# Ubuntu 18.04). Read out bytes individually.
|
|
def win_read(start, length):
|
|
try:
|
|
return b''.join(bar4_mmap[WINSTREAM_OFFSET + x].to_bytes(1, 'little')
|
|
for x in range(start, start + length))
|
|
except IndexError as ie:
|
|
# A FW in a bad state may cause winstream garbage
|
|
log.error("IndexError in bar4_mmap[%d + %d]", WINSTREAM_OFFSET, start)
|
|
log.error("bar4_mmap.size()=%d", bar4_mmap.size())
|
|
raise ie
|
|
|
|
def win_hdr():
|
|
return struct.unpack("<IIII", win_read(0, 16))
|
|
|
|
# Python implementation of the same algorithm in sys_winstream_read(),
|
|
# see there for details.
|
|
def winstream_read(last_seq):
|
|
while True:
|
|
(wlen, start, end, seq) = win_hdr()
|
|
if last_seq == 0:
|
|
last_seq = seq if args.no_history else (seq - ((end - start) % wlen))
|
|
if seq == last_seq or start == end:
|
|
return (seq, "")
|
|
behind = seq - last_seq
|
|
if behind > ((end - start) % wlen):
|
|
return (seq, "")
|
|
copy = (end - behind) % wlen
|
|
suffix = min(behind, wlen - copy)
|
|
result = win_read(16 + copy, suffix)
|
|
if suffix < behind:
|
|
result += win_read(16, behind - suffix)
|
|
(wlen, start1, end, seq1) = win_hdr()
|
|
if start1 == start and seq1 == seq:
|
|
# Best effort attempt at decoding, replacing unusable characters
|
|
# Found to be useful when it really goes wrong
|
|
return (seq, result.decode("utf-8", "replace"))
|
|
|
|
|
|
async def ipc_delay_done():
|
|
await asyncio.sleep(0.1)
|
|
dsp.HIPCTDA = 1<<31
|
|
|
|
ipc_timestamp = 0
|
|
|
|
# Super-simple command language, driven by the test code on the DSP
|
|
def ipc_command(data, ext_data):
|
|
send_msg = False
|
|
done = True
|
|
log.debug ("ipc data %d, ext_data %x", data, ext_data)
|
|
if data == 0: # noop, with synchronous DONE
|
|
pass
|
|
elif data == 1: # async command: signal DONE after a delay (on 1.8+)
|
|
if not cavs15:
|
|
done = False
|
|
asyncio.ensure_future(ipc_delay_done())
|
|
elif data == 2: # echo back ext_data as a message command
|
|
send_msg = True
|
|
elif data == 3: # set ADSPCS
|
|
dsp.ADSPCS = ext_data
|
|
elif data == 4: # echo back microseconds since last timestamp command
|
|
global ipc_timestamp
|
|
t = round(time.time() * 1e6)
|
|
ext_data = t - ipc_timestamp
|
|
ipc_timestamp = t
|
|
send_msg = True
|
|
elif data == 5: # copy word at outbox[ext_data >> 16] to inbox[ext_data & 0xffff]
|
|
src = OUTBOX_OFFSET + 4 * (ext_data >> 16)
|
|
dst = INBOX_OFFSET + 4 * (ext_data & 0xffff)
|
|
for i in range(4):
|
|
bar4_mmap[dst + i] = bar4_mmap[src + i]
|
|
elif data == 6: # HDA RESET (init if not exists)
|
|
stream_id = ext_data & 0xff
|
|
if stream_id in hda_streams:
|
|
hda_streams[stream_id].reset()
|
|
else:
|
|
hda_str = HDAStream(stream_id)
|
|
hda_streams[stream_id] = hda_str
|
|
elif data == 7: # HDA CONFIG
|
|
stream_id = ext_data & 0xFF
|
|
buf_len = ext_data >> 8 & 0xFFFF
|
|
hda_str = hda_streams[stream_id]
|
|
hda_str.config(buf_len)
|
|
elif data == 8: # HDA START
|
|
stream_id = ext_data & 0xFF
|
|
hda_streams[stream_id].start()
|
|
hda_streams[stream_id].mem.seek(0)
|
|
|
|
elif data == 9: # HDA STOP
|
|
stream_id = ext_data & 0xFF
|
|
hda_streams[stream_id].stop()
|
|
elif data == 10: # HDA VALIDATE
|
|
stream_id = ext_data & 0xFF
|
|
hda_str = hda_streams[stream_id]
|
|
hda_str.debug()
|
|
is_ramp_data = True
|
|
hda_str.mem.seek(0)
|
|
for (i, val) in enumerate(hda_str.mem.read(256)):
|
|
if i != val:
|
|
is_ramp_data = False
|
|
# log.info("stream[%d][%d]: %d", stream_id, i, val) # debug helper
|
|
log.info("Is ramp data? " + str(is_ramp_data))
|
|
ext_data = int(is_ramp_data)
|
|
log.info(f"Ext data to send back on ramp status {ext_data}")
|
|
send_msg = True
|
|
elif data == 11: # HDA HOST OUT SEND
|
|
stream_id = ext_data & 0xff
|
|
buf = bytearray(256)
|
|
for i in range(0, 256):
|
|
buf[i] = i
|
|
hda_streams[stream_id].write(buf)
|
|
elif data == 12: # HDA PRINT
|
|
log.info("Doing HDA Print")
|
|
stream_id = ext_data & 0xFF
|
|
buf_len = ext_data >> 8 & 0xFFFF
|
|
hda_str = hda_streams[stream_id]
|
|
pos = hda_str.mem.tell()
|
|
buf_data = hda_str.mem.read(buf_len).decode("utf-8", "replace")
|
|
log.info(f"DSP LOG MSG (idx: {pos}, len: {buf_len}): {buf_data}")
|
|
pos = hda_str.mem.tell()
|
|
if pos >= hda_str.buf_len*2:
|
|
log.info(f"Wrapping log reader, pos {pos} len {hda_str.buf_len}")
|
|
hda_str.mem.seek(0)
|
|
else:
|
|
log.warning(f"cavstool: Unrecognized IPC command 0x{data:x} ext 0x{ext_data:x}")
|
|
|
|
dsp.HIPCTDR = 1<<31 # Ack local interrupt, also signals DONE on v1.5
|
|
if cavs18:
|
|
time.sleep(0.01) # Needed on 1.8, or the command below won't send!
|
|
|
|
if done and not cavs15:
|
|
dsp.HIPCTDA = 1<<31 # Signal done
|
|
if send_msg:
|
|
dsp.HIPCIDD = ext_data
|
|
dsp.HIPCIDR = (1<<31) | ext_data
|
|
|
|
async def _main(server):
|
|
#TODO this bit me, remove the globals, write a little FirmwareLoader class or something to contain.
|
|
global hda, sd, dsp, hda_ostream_id, hda_streams
|
|
global start_output
|
|
try:
|
|
(hda, sd, dsp, hda_ostream_id) = map_regs()
|
|
except Exception as e:
|
|
log.error("Could not map device in sysfs; run as root?")
|
|
log.error(e)
|
|
sys.exit(1)
|
|
|
|
log.info(f"Detected cAVS {'1.5' if cavs15 else '1.8+'} hardware")
|
|
|
|
if args.log_only:
|
|
wait_fw_entered()
|
|
else:
|
|
if not fw_file:
|
|
log.error("Firmware file argument missing")
|
|
sys.exit(1)
|
|
|
|
load_firmware(fw_file)
|
|
time.sleep(0.1)
|
|
if not args.quiet:
|
|
adsp_log("--\n", server)
|
|
|
|
hda_streams = dict()
|
|
|
|
last_seq = 0
|
|
while start_output is True:
|
|
await asyncio.sleep(0.03)
|
|
(last_seq, output) = winstream_read(last_seq)
|
|
if output:
|
|
adsp_log(output, server)
|
|
if dsp.HIPCIDA & 0x80000000:
|
|
dsp.HIPCIDA = 1<<31 # must ACK any DONE interrupts that arrive!
|
|
if dsp.HIPCTDR & 0x80000000:
|
|
ipc_command(dsp.HIPCTDR & ~0x80000000, dsp.HIPCTDD)
|
|
|
|
if server:
|
|
# Check if the client connection is alive.
|
|
if not is_connection_alive(server):
|
|
lock.acquire()
|
|
start_output = False
|
|
lock.release()
|
|
|
|
class adsp_request_handler(socketserver.BaseRequestHandler):
|
|
"""
|
|
The request handler class for control the actions of server.
|
|
"""
|
|
|
|
def receive_fw(self):
|
|
log.info("Receiving...")
|
|
# Receive the header first
|
|
d = self.request.recv(HEADER_SZ)
|
|
|
|
# Unpacked the header data
|
|
# Include size(4), filename(42) and MD5(32)
|
|
header = d[:HEADER_SZ]
|
|
total = d[HEADER_SZ:]
|
|
s = struct.Struct(PACKET_HEADER_FORMAT_FW)
|
|
fsize, fname, md5_tx_b = s.unpack(header)
|
|
log.info(f'size:{fsize}, filename:{fname}, MD5:{md5_tx_b}')
|
|
|
|
# Receive the firmware. We only receive the specified amount of bytes.
|
|
while len(total) < fsize:
|
|
data = self.request.recv(min(BUF_SIZE, fsize - len(total)))
|
|
if not data:
|
|
raise EOFError("truncated firmware file")
|
|
total += data
|
|
|
|
log.info(f"Done Receiving {len(total)}.")
|
|
|
|
try:
|
|
with open(fname,'wb') as f:
|
|
f.write(total)
|
|
except Exception as e:
|
|
log.error(f"Get exception {e} during FW transfer.")
|
|
return None
|
|
|
|
# Check the MD5 of the firmware
|
|
md5_rx = hashlib.md5(total).hexdigest()
|
|
md5_tx = md5_tx_b.decode('utf-8')
|
|
|
|
if md5_tx != md5_rx:
|
|
log.error(f'MD5 mismatch: {md5_tx} vs. {md5_rx}')
|
|
return None
|
|
|
|
return fname
|
|
|
|
def handle(self):
|
|
global start_output, fw_file
|
|
|
|
cmd = self.request.recv(MAX_CMD_SZ)
|
|
log.info(f"{self.client_address[0]} wrote: {cmd}")
|
|
action = cmd.decode("utf-8")
|
|
log.debug(f'load {action}')
|
|
|
|
if action == CMD_DOWNLOAD:
|
|
self.request.sendall(cmd)
|
|
recv_file = self.receive_fw()
|
|
|
|
if recv_file:
|
|
self.request.sendall("success".encode('utf-8'))
|
|
log.info("Firmware well received. Ready to download.")
|
|
else:
|
|
self.request.sendall("failed".encode('utf-8'))
|
|
log.error("Receive firmware failed.")
|
|
|
|
lock.acquire()
|
|
fw_file = recv_file
|
|
start_output = True
|
|
lock.release()
|
|
|
|
else:
|
|
log.error("incorrect load communitcation!")
|
|
|
|
class adsp_log_handler(socketserver.BaseRequestHandler):
|
|
"""
|
|
The log handler class for grabbing output messages of server.
|
|
"""
|
|
def run_adsp(self):
|
|
self.loop = asyncio.get_event_loop()
|
|
self.loop.run_until_complete(_main(self))
|
|
|
|
def handle(self):
|
|
cmd = self.request.recv(MAX_CMD_SZ)
|
|
log.info(f"{self.client_address[0]} wrote: {cmd}")
|
|
action = cmd.decode("utf-8")
|
|
log.debug(f'monitor {action}')
|
|
|
|
if action == CMD_LOG_START:
|
|
global start_output, fw_file
|
|
|
|
self.request.sendall(cmd)
|
|
|
|
log.info(f"Waiting for instruction...")
|
|
while start_output is False:
|
|
time.sleep(1)
|
|
if not is_connection_alive(self):
|
|
break
|
|
|
|
if fw_file:
|
|
log.info(f"Loaded FW {fw_file} and running...")
|
|
if os.path.exists(fw_file):
|
|
self.run_adsp()
|
|
log.info("service complete.")
|
|
else:
|
|
log.error("Cannot find the FW file.")
|
|
|
|
lock.acquire()
|
|
start_output = False
|
|
if fw_file:
|
|
os.remove(fw_file)
|
|
fw_file = None
|
|
lock.release()
|
|
|
|
else:
|
|
log.error("incorrect monitor communitcation!")
|
|
|
|
log.info("Wait for next service...")
|
|
|
|
def is_connection_alive(server):
|
|
try:
|
|
server.request.sendall(b' ')
|
|
except (BrokenPipeError, ConnectionResetError):
|
|
log.info("Client is disconnect.")
|
|
return False
|
|
|
|
return True
|
|
|
|
def adsp_log(output, server):
|
|
if server:
|
|
server.request.sendall(output.encode("utf-8"))
|
|
else:
|
|
sys.stdout.write(output)
|
|
sys.stdout.flush()
|
|
|
|
def get_host_ip():
|
|
"""
|
|
Helper tool use to detect host's serving ip address.
|
|
"""
|
|
interfaces = netifaces.interfaces()
|
|
|
|
for i in interfaces:
|
|
if i != "lo":
|
|
try:
|
|
netifaces.ifaddresses(i)
|
|
ip = netifaces.ifaddresses(i)[netifaces.AF_INET][0]['addr']
|
|
log.info (f"Use interface {i}, IP address: {ip}")
|
|
except Exception:
|
|
log.info(f"Ignore the interface {i} which is not activated.")
|
|
return ip
|
|
|
|
|
|
ap = argparse.ArgumentParser(description="DSP loader/logger tool")
|
|
ap.add_argument("-q", "--quiet", action="store_true",
|
|
help="No loader output, just DSP logging")
|
|
ap.add_argument("-l", "--log-only", action="store_true",
|
|
help="Don't load firmware, just show log output")
|
|
ap.add_argument("-n", "--no-history", action="store_true",
|
|
help="No current log buffer at start, just new output")
|
|
ap.add_argument("-s", "--server-addr",
|
|
help="Specify the IP address that the server to active")
|
|
ap.add_argument("fw_file", nargs="?", help="Firmware file")
|
|
|
|
args = ap.parse_args()
|
|
|
|
if args.quiet:
|
|
log.setLevel(logging.WARN)
|
|
|
|
if args.fw_file:
|
|
fw_file = args.fw_file
|
|
else:
|
|
fw_file = None
|
|
|
|
if args.server_addr:
|
|
HOST = args.server_addr
|
|
else:
|
|
HOST = get_host_ip()
|
|
|
|
if __name__ == "__main__":
|
|
|
|
# When fw_file is assigned or in log_only mode, it will
|
|
# not serve as a daemon. That mean it just run load
|
|
# firmware or read the log directly.
|
|
if args.fw_file or args.log_only:
|
|
start_output = True
|
|
try:
|
|
asyncio.get_event_loop().run_until_complete(_main(None))
|
|
except KeyboardInterrupt:
|
|
start_output = False
|
|
finally:
|
|
sys.exit(0)
|
|
|
|
# Launch the command request service
|
|
socketserver.TCPServer.allow_reuse_address = True
|
|
req_server = socketserver.TCPServer((HOST, PORT_REQ), adsp_request_handler)
|
|
req_t = threading.Thread(target=req_server.serve_forever, daemon=True)
|
|
|
|
# Activate the log service which output adsp execution
|
|
with socketserver.TCPServer((HOST, PORT_LOG), adsp_log_handler) as log_server:
|
|
try:
|
|
log.info("Req server start...")
|
|
req_t.start()
|
|
log.info("Log server start...")
|
|
log_server.serve_forever()
|
|
except KeyboardInterrupt:
|
|
lock.acquire()
|
|
start_output = False
|
|
lock.release()
|
|
log_server.shutdown()
|
|
req_server.shutdown()
|