e4a455b25d
General refactoring to clean up and futureproof this driver. Remove false dependency on CONFIG_CAVS_ICTL. This requires the CAVS interrupt mask API, but doesn't touch the interrupt controller driver. Remove a racy check for simultaneous interrupts. This seems to have been well intentioned, but it's needless: the spinlock around the last_count computation guarantees that colliding interrupts will correctly compute elapsed ticks (i.e. the last will compute and announce zero ticks, which is correct and expected). And this opened a tiny window where you could incorrectly ignore a just-set timeout. Factor out the specific registers used (there are only five) into pointer-valued macros instead of banging them directly. Unify interrupt initialization for main and auxiliary cores. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
15 lines
571 B
Text
15 lines
571 B
Text
# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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config CAVS_TIMER
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bool "CAVS DSP Wall Clock Timer on Intel SoC"
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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The DSP wall clock timer is a timer driven directly by
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external oscillator and is external to the CPU core(s).
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It is not as fast as the internal core clock, but provides
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a common and synchronized counter for all CPU cores (which
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is useful for SMP).
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