zephyr/soc/riscv
Dino Li 003e0be6fb it8xxx2/linker: append h2ram_pool section at the end of used memory
Since __sha256_ram_block section must in the first 4KB,
h2ram_pool section is no longer included first inside the
RAMABLE_REGION.
Append h2ram_pool section at the end of used memory, so gap
due to alignment is still available for newly added variables.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-08-31 10:20:17 +02:00
..
espressif_esp32 soc: riscv|xtensa: esp32: add support for sys_poweroff 2023-08-15 10:15:38 -07:00
litex-vexriscv soc: riscv: Add ability to use custom sys_io functions 2023-07-26 09:43:59 +02:00
openisa_rv32m1 include/zephyr: Fix linker scripts to define _end after all static RAM data 2023-06-28 08:41:02 +00:00
riscv-ite it8xxx2/linker: append h2ram_pool section at the end of used memory 2023-08-31 10:20:17 +02:00
riscv-privileged soc: riscv: telink_b91: add missing init.h, devicetree.h 2023-08-30 11:51:57 +02:00
CMakeLists.txt riscv32: rename to riscv 2019-08-02 13:54:48 -07:00