e77ea215bd
Add hwinfo driver for Silicon Labs Series 2 devices. The driver is separate from the Series 0/1 Gecko driver because the available reset causes are completely different. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
124 lines
3 KiB
C
124 lines
3 KiB
C
/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/hwinfo.h>
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#include <zephyr/sys/byteorder.h>
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#include <string.h>
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#include <em_system.h>
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#include <em_rmu.h>
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/* Ensure that all possible reset causes have a definition */
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#ifndef EMU_RSTCAUSE_BOOSTON
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#define EMU_RSTCAUSE_BOOSTON 0
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#endif
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#ifndef EMU_RSTCAUSE_WDOG1
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#define EMU_RSTCAUSE_WDOG1 0
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#endif
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#ifndef EMU_RSTCAUSE_IOVDD1BOD
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#define EMU_RSTCAUSE_IOVDD1BOD 0
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#endif
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#ifndef EMU_RSTCAUSE_IOVDD2BOD
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#define EMU_RSTCAUSE_IOVDD2BOD 0
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#endif
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#ifndef EMU_RSTCAUSE_SETAMPER
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#define EMU_RSTCAUSE_SETAMPER 0
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#endif
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#ifndef EMU_RSTCAUSE_SESYSREQ
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#define EMU_RSTCAUSE_SESYSREQ 0
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#endif
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#ifndef EMU_RSTCAUSE_SELOCKUP
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#define EMU_RSTCAUSE_SELOCKUP 0
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#endif
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#ifndef EMU_RSTCAUSE_DCI
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#define EMU_RSTCAUSE_DCI 0
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#endif
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/* The Zephyr API expects hwinfo_get_reset_cause() to return 0 after hwinfo_clear_reset_cause() has
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* been called. This matches the hardware behavior on Series 2, but not the HAL API. The HAL stores
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* the reset cause upon first read, and returns this cached value on subsequent calls to the API
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* to allow multiple subsystems to read the reset cause despite it having been cleared in hardware
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* already. Emulate the hardware behavior while staying compatible with other users of the HAL API
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* by keeping track of whether the reset cause should be considered cleared or not ourselves.
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*/
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static bool reset_cleared;
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ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
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{
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uint64_t unique_id = sys_cpu_to_be64(SYSTEM_GetUnique());
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if (length > sizeof(unique_id)) {
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length = sizeof(unique_id);
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}
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memcpy(buffer, &unique_id, length);
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return length;
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}
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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uint32_t rmu = RMU_ResetCauseGet();
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if (reset_cleared) {
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*cause = 0;
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return 0;
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}
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if (rmu & EMU_RSTCAUSE_POR) {
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flags |= RESET_POR;
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}
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if (rmu & EMU_RSTCAUSE_PIN) {
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flags |= RESET_PIN;
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}
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if (rmu & (EMU_RSTCAUSE_EM4 | EMU_RSTCAUSE_BOOSTON)) {
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flags |= RESET_LOW_POWER_WAKE;
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}
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if (rmu & (EMU_RSTCAUSE_WDOG0 | EMU_RSTCAUSE_WDOG1)) {
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flags |= RESET_WATCHDOG;
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}
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if (rmu & EMU_RSTCAUSE_LOCKUP) {
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flags |= RESET_CPU_LOCKUP;
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}
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if (rmu & EMU_RSTCAUSE_SYSREQ) {
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flags |= RESET_SOFTWARE;
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}
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if (rmu & (EMU_RSTCAUSE_DVDDBOD | EMU_RSTCAUSE_DVDDLEBOD | EMU_RSTCAUSE_DECBOD |
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EMU_RSTCAUSE_AVDDBOD | EMU_RSTCAUSE_IOVDD0BOD |
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EMU_RSTCAUSE_IOVDD1BOD | EMU_RSTCAUSE_IOVDD2BOD)) {
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flags |= RESET_BROWNOUT;
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}
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if (rmu & (EMU_RSTCAUSE_SETAMPER | EMU_RSTCAUSE_SESYSREQ |
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EMU_RSTCAUSE_SELOCKUP | EMU_RSTCAUSE_DCI)) {
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flags |= RESET_SECURITY;
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}
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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RMU_ResetCauseClear();
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reset_cleared = true;
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = RESET_PIN | RESET_SOFTWARE | RESET_BROWNOUT | RESET_POR | RESET_WATCHDOG |
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RESET_SECURITY | RESET_LOW_POWER_WAKE | RESET_CPU_LOCKUP;
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return 0;
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}
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