e5e73a70e9
Many ARM SoCs included <devicetree.h> likely due to: 1. nvic.h not being self-contained 2. As a result of copy-paste Some RISC-V SoCs had the same problem, in this case likely due to copy-paste from ARM. The <devicetree.h> header has been removed using the following command: sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h soc.h files that make a legitimate usage of the API have not been changed. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
62 lines
2.5 KiB
C
62 lines
2.5 KiB
C
/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef RISCV_NEORV32_SOC_H
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#define RISCV_NEORV32_SOC_H
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#include <soc_common.h>
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/* Machine System Timer (MTIME) registers */
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#define RISCV_MTIME_BASE 0xffffff90U
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#define RISCV_MTIMECMP_BASE 0xffffff98U
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/* System information (SYSINFO) register offsets */
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#define NEORV32_SYSINFO_CLK 0x00U
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#define NEORV32_SYSINFO_CPU 0x04U
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#define NEORV32_SYSINFO_FEATURES 0x08U
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#define NEORV32_SYSINFO_CACHE 0x0cU
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#define NEORV32_SYSINFO_ISPACE_BASE 0xf0U
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#define NEORV32_SYSINFO_IMEM_SIZE 0xf4U
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#define NEORV32_SYSINFO_DSPACE_BASE 0xf8U
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#define NEORV32_SYSINFO_DMEM_SIZE 0xfcU
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/* System information (SYSINFO) CPU register bits */
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#define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
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#define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
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#define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
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#define NEORV32_SYSINFO_CPU_ZBB BIT(3)
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#define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
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#define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
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#define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
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#define NEORV32_SYSINFO_CPU_PMP BIT(8)
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#define NEORV32_SYSINFO_CPU_HPM BIT(9)
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#define NEORV32_SYSINFO_CPU_DEBUGMODE BIT(10)
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#define NEORV32_SYSINFO_CPU_FASTMUL BIT(30)
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#define NEORV32_SYSINFO_CPU_FASTSHIFT BIT(31)
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/* System information (SYSINFO) FEATURES register bits */
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#define NEORV32_SYSINFO_FEATURES_BOOTLOADER BIT(0)
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#define NEORV32_SYSINFO_FEATURES_MEM_EXT BIT(1)
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#define NEORV32_SYSINFO_FEATURES_MEM_INT_IMEM BIT(2)
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#define NEORV32_SYSINFO_FEATURES_MEM_INT_DMEM BIT(3)
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#define NEORV32_SYSINFO_FEATURES_MEM_EXT_ENDIAN BIT(4)
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#define NEORV32_SYSINFO_FEATURES_ICACHE BIT(5)
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#define NEORV32_SYSINFO_FEATURES_OCD BIT(14)
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#define NEORV32_SYSINFO_FEATURES_HW_RESET BIT(15)
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#define NEORV32_SYSINFO_FEATURES_IO_GPIO BIT(16)
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#define NEORV32_SYSINFO_FEATURES_IO_MTIME BIT(17)
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#define NEORV32_SYSINFO_FEATURES_IO_UART0 BIT(18)
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#define NEORV32_SYSINFO_FEATURES_IO_SPI BIT(19)
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#define NEORV32_SYSINFO_FEATURES_IO_TWI BIT(20)
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#define NEORV32_SYSINFO_FEATURES_IO_PWM BIT(21)
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#define NEORV32_SYSINFO_FEATURES_IO_WDT BIT(22)
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#define NEORV32_SYSINFO_FEATURES_IO_CFS BIT(23)
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#define NEORV32_SYSINFO_FEATURES_IO_TRNG BIT(24)
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#define NEORV32_SYSINFO_FEATURES_IO_SLINK BIT(25)
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#define NEORV32_SYSINFO_FEATURES_IO_UART1 BIT(26)
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#define NEORV32_SYSINFO_FEATURES_IO_NEOLED BIT(27)
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#endif /* RISCV_NEORV32_SOC_H */
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