e5e73a70e9
Many ARM SoCs included <devicetree.h> likely due to: 1. nvic.h not being self-contained 2. As a result of copy-paste Some RISC-V SoCs had the same problem, in this case likely due to copy-paste from ARM. The <devicetree.h> header has been removed using the following command: sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h soc.h files that make a legitimate usage of the API have not been changed. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* Copyright (c) 2017 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ATMEL_SAMR21_SOC_H_
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#define ZEPHYR_ATMEL_SAMR21_SOC_H_
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#ifndef _ASMLANGUAGE
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#define DONT_USE_CMSIS_INIT
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#include <zephyr/types.h>
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#if defined(CONFIG_SOC_PART_NUMBER_SAMR21E16A)
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#include <samr21e16a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E17A)
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#include <samr21e17a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E18A)
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#include <samr21e18a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E19A)
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#include <samr21e19a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G16A)
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#include <samr21g16a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G17A)
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#include <samr21g17a.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G18A)
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#include <samr21g18a.h>
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#else
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#error Library does not support the specified device.
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#endif
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#endif /* _ASMLANGUAGE */
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#include "../common/soc_port.h"
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#include "../common/atmel_sam0_dt.h"
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/** Processor Clock (HCLK) Frequency */
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#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
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/** Master Clock (MCK) Frequency */
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#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
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#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000
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#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#if defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#else
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#error Unsupported GCLK1 clock source.
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#endif
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#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#endif /* ZEPHYR_ATMEL_SAMR21_SOC_H_ */
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