zephyr/arch
Daniel Leung 5539c3ed90 xtensa: add calling entry point for multi-processing
Under multi-processing, only the first CPU#0 needs to go through
setting up the kernel structs and clearing out BSS (among others).
There is no need for other CPUs to do those tasks. Since each
Xtensa core starts using the same boot vector, CPUs other than #0
need to skip all the startup tasks by not calling to z_cstart().
So provide another entry point for those CPUs. Note that Xtensa
arch is highly configurable. So the implementation of the entry
point is up to each individual SoC config.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-03-25 19:07:28 -04:00
..
arc kernel: interrupt/idle stacks/threads as array 2020-03-16 23:17:36 +02:00
arm arch: aarch64: Add check on context switch 2020-03-23 12:13:07 +01:00
common isr_tables: Support hardware interrupt vector table-only configuration. 2020-03-13 12:02:03 +01:00
nios2 kernel: interrupt/idle stacks/threads as array 2020-03-16 23:17:36 +02:00
posix tracing: move headers under include/tracing 2020-02-07 15:58:05 -05:00
riscv kernel: interrupt/idle stacks/threads as array 2020-03-16 23:17:36 +02:00
x86 kernel: interrupt/idle stacks/threads as array 2020-03-16 23:17:36 +02:00
xtensa xtensa: add calling entry point for multi-processing 2020-03-25 19:07:28 -04:00
CMakeLists.txt arch: Simplify private header include path configuration. 2019-11-06 16:07:32 -08:00
Kconfig kernel: delete separate logic for priv stacks 2020-03-17 20:11:27 +02:00