e039053546
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_
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#include <drivers/pcie/pcie.h>
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#include <zephyr/types.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Find a PCI(e) capability in an endpoint's configuration space.
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*
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* @param bdf the PCI endpoint to examine
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* @param cap_id the capability ID of interest
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* @return the index of the configuration word, or 0 if no capability.
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*
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* Note: PCI(e) capabilities are only used in the MSI code, so for
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* now, capabilities-related code is only included when MSI is. It
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* can easily be separated out if/when its use spreads.
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*/
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extern u32_t pcie_get_cap(pcie_bdf_t bdf, u32_t cap_id);
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/*
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* Configuration word 13 contains the head of the capabilities list.
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*/
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#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */
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#define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)
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/*
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* The first word of every capability contains a capability identifier,
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* and a link to the next capability (or 0) in configuration space.
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*/
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#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
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#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
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/**
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* @brief Compute the target address for an MSI posted write.
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*
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* This function is exported by the arch, board or SoC code.
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*
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* @param irq The IRQ we wish to trigger via MSI.
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* @return A (32-bit) value for the MSI MAP register.
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*/
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extern u32_t pcie_msi_map(unsigned int irq);
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/**
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* @brief Compute the data for an MSI posted write.
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*
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* This function is exported by the arch, board or SoC code.
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*
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* @param irq The IRQ we wish to trigger via MSI.
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* @return A (16-bit) value for MSI MDR register.
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*/
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extern u16_t pcie_msi_mdr(unsigned int irq);
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/**
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* @brief Configure the given PCI endpoint to generate MSIs.
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*
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* @param bdf the target PCI endpoint
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* @param irq the IRQ which should be generated
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* @return true if the endpoint supports MSI, false otherwise.
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*/
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extern bool pcie_set_msi(pcie_bdf_t bdf, unsigned int irq);
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/*
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* MSI capability ID in the PCI configuration capability list.
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*/
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#define PCIE_MSI_CAP_ID 05U
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/*
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* The first word of the MSI capability is shared with the
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* capability ID and list link. The high 16 bits are the MCR.
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*/
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#define PCIE_MSI_MCR 0U
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#define PCIE_MSI_MCR_EN 0x00010000U /* enable MSI */
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#define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
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#define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
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/*
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* The MAP follows the MCR. If PCIE_MSI_MCR_64, then the MAP
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* is two words long. The MDR follows immediately after the MAP.
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*/
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#define PCIE_MSI_MAP0 1U
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#define PCIE_MSI_MAP1_64 2U
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#define PCIE_MSI_MDR_32 2U
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#define PCIE_MSI_MDR_64 3U
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_MSI_H_ */
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