df21ab8541
Since all the L4 SoCs are using DTS we can remove the various Kconfig bits that we now get from DTS. Change-Id: Icdec49b478ff285dc3347b09412964a721f75bbf Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
59 lines
1.3 KiB
Text
59 lines
1.3 KiB
Text
CONFIG_ARM=y
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CONFIG_BOARD_STM32_NUCLEO_L476RG=y
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CONFIG_SOC_FAMILY_STM32=y
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CONFIG_SOC_SERIES_STM32L4X=y
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CONFIG_SOC_STM32L476XX=y
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CONFIG_CORTEX_M_SYSTICK=y
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# 80MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
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# enable uart driver
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CONFIG_SERIAL=y
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CONFIG_UART_STM32=y
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CONFIG_UART_STM32_PORT_2=y
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# enable pinmux
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CONFIG_PINMUX=y
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CONFIG_PINMUX_STM32=y
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# enable GPIOs
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CONFIG_GPIO=y
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CONFIG_GPIO_STM32=y
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CONFIG_GPIO_STM32_PORTA=y
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CONFIG_GPIO_STM32_PORTB=y
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CONFIG_GPIO_STM32_PORTC=y
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CONFIG_GPIO_STM32_PORTD=y
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CONFIG_GPIO_STM32_PORTE=y
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CONFIG_GPIO_STM32_PORTF=y
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CONFIG_GPIO_STM32_PORTG=y
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CONFIG_GPIO_STM32_PORTH=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL_STM32_CUBE=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# PLL configuration
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CONFIG_CLOCK_STM32_PLL_SRC_HSI
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# produce 80MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=4
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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# console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
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#enable pwm
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CONFIG_PWM=y
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CONFIG_PWM_STM32=y
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CONFIG_PWM_STM32_2=y
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#enable DTS
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CONFIG_HAS_DTS=y
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