dea2e642b2
Add pin control support for IOMUXC peripheral present on mimx8ml8_m7 soc. This reuses the existing pin control driver for the IOMUXC peripheral, but uses a new header and compatible binding to handle the different register layout on this SOC. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
50 lines
1.1 KiB
Text
50 lines
1.1 KiB
Text
# i.MX8ML M7 SoC series
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# Copyright (c) 2021, Laird Connectivity
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "i.MX8ML M7 Selection"
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depends on SOC_SERIES_IMX8ML_M7
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config SOC_MIMX8ML8
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bool "SOC_MIMX8ML8"
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select HAS_MCUX
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select HAS_MCUX_CCM
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select HAS_MCUX_RDC
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select ARM_MPU
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select HAS_MCUX_IGPIO
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select HAS_MCUX_IOMUXC
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endchoice
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if SOC_SERIES_IMX8ML_M7
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config SOC_PART_NUMBER_MIMX8ML8DVNLZ
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bool
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config SOC_PART_NUMBER_IMX8ML_M7
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string
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default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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choice CODE_LOCATION
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prompt "Code location selection"
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config CODE_ITCM
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bool "Link code into internal instruction tightly coupled memory (ITCM)"
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config CODE_DDR
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bool "Link code into DDR memory"
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endchoice
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config INIT_VIDEO_PLL
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bool "Initialize Video PLL"
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endif # SOC_SERIES_IMX8ML_M7
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