de13103f0b
Add .. zephyr:board-supported-runners:: to the Programming and Debugging section of the documentation for each board that has one such section, as this is the most natural place to put it. Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
444 lines
51 KiB
ReStructuredText
444 lines
51 KiB
ReStructuredText
.. zephyr:board:: max78002evkit
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Overview
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********
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The MAX78002 evaluation kit (EV kit) provides a platform and tools for leveraging device capabilities to build new
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generations of artificial intelligence (AI) products.
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The kit provides optimal versatility with a modular peripheral architecture, allowing a variety of input and output
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devices to be remotely located. DVP and CSI cameras, I2S audio peripherals, digital microphones, and analog sensors
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are supported, while a pair of industry-standard QWIIC connectors supports a large and growing array of aftermarket
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development boards. An onboard stereo audio codec offers line-level audio input and output, and tactile input is
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provided by a touch-enabled 2.4in TFT display. The MAX78002 energy consumption is tracked by a power accumulator,
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with four channels of formatted results presented on a secondary TFT display. All device GPIOs are accessible on
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0.1in pin headers. A standard coaxial power jack serves as power input, using the included 5V, 3A wall-mount
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adapter. Two USB connectors provide serial access to the MAX78002, one directly and the other through a USB to UART
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bridge. A third USB connector allows access to the MAX78002 energy consumption data. Rounding out the features, a
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microSD connector provides the capability for inexpensive highdensity portable data storage.
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The Zephyr port is running on the MAX78002 MCU.
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.. image:: img/max78002evkit.webp
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:align: center
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:alt: MAX78002 EVKIT Front
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.. image:: img/max78002evkit_back.webp
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:align: center
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:alt: MAX78002 EVKIT Back
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Hardware
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********
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- MAX78002 MCU:
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- Dual-Core, Low-Power Microcontroller
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- Arm Cortex-M4 Processor with FPU up to 120MHz
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- 2.5MB Flash, 64KB ROM, and 384KB SRAM
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- Optimized Performance with 16KB Instruction Cache
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- Optional Error Correction Code (ECC SEC-DED) for SRAM
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- 32-Bit RISC-V Coprocessor up to 60MHz
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- Up to 60 General-Purpose I/O Pins
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- MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1
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- Support for Two Data Lanes
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- 12-Bit Parallel Camera Interface
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- I2S Controller/Target for Digital Audio Interface
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- Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51
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- Convolutional Neural Network (CNN) Accelerator
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- Highly Optimized for Deep CNNs
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- 2 Million 8-Bit Weight Capacity with 1-, 2-, 4-, and 8-bit Weights
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- 1.3MB CNN Data Memory
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- Programmable Input Image Size up to 2048 x 2048 Pixels
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- Programmable Network Depth up to 128 Layers
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- Programmable per Layer Network Channel Widths up to 1024 Channels
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- 1- and 2-Dimensional Convolution Processing
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- Capable of Processing VGA Images at 30fps
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- Power Management for Extending Battery Life
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- Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)
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- 2.85V to 3.6V Supply Voltage Range
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- Support of Optional External Auxiliary CNN Power Supply
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- Dynamic Voltage Scaling Minimizes Active Core Power Consumption
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- 23.9μA/MHz While Loop Execution at 3.3V from Cache (CM4 only)
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- Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled
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- Security and Integrity
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- Available Secure Boot
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- AES 128/192/256 Hardware Acceleration Engine
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- True Random Number Generator (TRNG) Seed Generator
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- External devices connected to the MAX78002 EVKIT:
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- Color TFT Display
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- Audio Stereo Codec Interface
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- Digital Microphone
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- A 8Mb QSPI ram
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| Name | Name | Settings | Description |
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+===========+===================+===============+==================================================================================================+
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| JP1 | 3V3 MON | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Normal operation in conjunction with JP3 jumpered 1-2 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Test access point for current measurement | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP2 | 3V3 SW PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for main 3.3 V system power are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Main 3.3V input routes through shunts for power accumulator measurements | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP3 | CNN MON | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Normal operation in conjunction with JP6 jumpered 1-2 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Test access point for current measurement of U4's share of VCOREA and CNN loads | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP4 | VCOREA PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREA + CNN loads route through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP5 | VCOREB PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for VCOREB are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREB power routes through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP6 | VREGO_A PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for VREGO_A are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VREGO_A power routes through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP7 | VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables 3V3 VBAT power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables 3V3 VBAT power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP8 | VREGI | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables 3V3 VREGI power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables 3V3 VREGI power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP9 | VREGI/VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Onboard 3V3_PM supplies VREGI/VBAT | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | External source at TP10 supplies VREGI/VBAT | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP10 | VDDIOH | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Onboard 3V3_PM supplies VDDIOH | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Onboard 3V3_SW supplies VDDIOH | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP11 | VDDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_A_PM powers VDDA | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VDDA may be powered using TP6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP12 | VDDIO | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_A_PM powers VDDIO | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VDDIO may be powered using TP7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP13 | VCOREB | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_B powers VCOREB | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREB may be powered using TP8 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP14 | VCOREA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_C ties to net VCOREA | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Net VCOREA may be powered using TP9; JP17 may also be used as a current test point | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP15 | VREF | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | DUT ADC VREF is supplied by precision external reference | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | External ADC VREF disabled; ref voltage may be injected at JP18.1 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP16 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 DATA pullup | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP17 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 CLOCK pullup | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP18 | TRIG1 | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | PWR accumulator trigger signal 1 ties to port 1.6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | TRIG1 is disabled, so DVP camera PCIF_D10 may be used instead | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP19 | TRIG2 | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | PWR accumulator trigger signal 2 ties to port 1.7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | TRIG2 is disabled, so DVP camera PCIF_D11 may be used instead | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP20 | UART0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Closed | | | USB-UART bridge connected to DUT UART0 (RTS and CTS are supported) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | USB-UART bridge disconnected from DUT UART0 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP21 | I2C0_SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C0 DATA pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP22 | I2C0_SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C0 CLOCK pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP23 | UART1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Closed | | | USB-UART bridge connected to DUT UART1 (no HW flow control) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | USB-UART bridge disconnected from DUT UART1 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP24 | EXT I2C0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | QWIIC interface for I2C0 enabled by default | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP25 | PB1 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN6) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP26 | PB2 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN7) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP27 | I2C2 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C2 DATA pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP28 | I2C2 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C2 CLOCK pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP29 | VDDB | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | DUT USB XCVR VDDB powered from VBUS regulated with dedicated 3.3V LDO | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | USB XCVR VDDB powered full time by system 3V3_PM | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP30 | EXT I2C2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | QWIIC interface for I2C2 enabled by default | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP31 | L/R SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | MIC ON R CH, I2S microphone data stream | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | MIC ON L CH, I2S microphone data stream | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP32 | MIC-I2S I/O | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | External I2S data from I2S I/O header connected to I2S SDI. | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | External MIC data from I2S MIC header connected to I2S SDI | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP33 | MIC-I2S/CODEC | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Onboard CODEC data connects to I2S SDI | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | External I2S data (mic or slave I2S) from header connects to I2S SDI | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP34 | I2S VDD | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | External MIC and DATA I2S interface headers run at 1.8V | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | External MIC and DATA I2S interface headers run at 3.3V | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP35 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 DATA pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP36 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 CLOCK pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP37 | I2S CK SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2S master clock sourced from SMA connector J6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | I2S master clock sourced from onboard crystal oscillator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP38 | DVP CAM PWR | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Sets state of DVP camera PWDN input; default is OFF for OVM7692 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Sets state of DVP camera PWDN input; 2-3 will power up OVM7692 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP39 | SW CAM PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Camera reset and power up under port pin control | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Digilent P5C camera powered down, JP39 can over ride this condition | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP40 | HW PWUP / SW PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Camera will reset and power up as soon as 3.3V reaches a valid level | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Camera reset and power up under port pin control if JP39 is installed; else, camera off | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP41 | CSI CAM I2C EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 1-2 | | | CSI camera Digilent P5C I2C connects to I2C1 for register setup | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | Open | | | Level translator and I2C PU are in high-Z state; I2C1 disconnected from P5C registers | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | |
|
|
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
|
| JP42 | TFT DC | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 1-2 | | | TFT data/command select connects to port 2.2 | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | Open | | | Pull jumper if using AIN2 | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | |
|
|
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
|
| JP43 | TFT CS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 2-1 | | | TFT CS driven by port 0.3, shared with UART0 RTS | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 2-3 | | | TFT CS driven by port 1.7, shared with DVP DATA 11 and TRIG2 | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | |
|
|
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
|
| JP44 | LED1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 1-2 | | | LED0 illuminates when port 2.4 is high | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | Open | | | Pull jumper if using AIN4 | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | |
|
|
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
|
| JP45 | LED2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | 1-2 | | | LED1 illuminates when port 2.5 is high | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | Open | | | Pull jumper if using AIN5 | |
|
|
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
|
| | | | |
|
|
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
|
|
|
Programming and Debugging
|
|
*************************
|
|
|
|
.. zephyr:board-supported-runners::
|
|
|
|
Flashing
|
|
========
|
|
|
|
The MAX78002 MCU can be flashed by connecting an external debug probe to the
|
|
SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH8.
|
|
Logic levels are fixed to VDDIO (1.8V).
|
|
|
|
Once the debug probe is connected to your host computer, then you can simply run the
|
|
``west flash`` command to write a firmware image into flash. To perform a full erase,
|
|
pass the ``--erase`` option when executing ``west flash``.
|
|
|
|
.. note::
|
|
|
|
This board uses OpenOCD as the default debug interface. You can also use
|
|
a Segger J-Link with Segger's native tooling by overriding the runner,
|
|
appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
|
|
be connected to the standard 2*5 pin debug connector (JH8) using an
|
|
appropriate adapter board and cable.
|
|
|
|
Debugging
|
|
=========
|
|
|
|
Please refer to the `Flashing`_ section and run the ``west debug`` command
|
|
instead of ``west flash``.
|
|
|
|
References
|
|
**********
|
|
|
|
- `MAX78002EVKIT web page`_
|
|
|
|
.. _MAX78002EVKIT web page:
|
|
https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
|