db6ca32346
These settings are used to put the pins in power saving mode when we enter SUSPEND power mode. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright 2022, 2024-25 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/pm/pm.h>
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#include <fsl_power.h>
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#include <fsl_common.h>
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#include <fsl_io_mux.h>
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#define NON_AON_PINS_START 0
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#define NON_AON_PINS_BREAK 21
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#define NON_AON_PINS_RESTART 28
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#define NON_AON_PINS_END 63
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#define RF_CNTL_PINS_START 0
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#define RF_CNTL_PINS_END 3
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static void rdrw61x_power_init_config(void)
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{
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power_init_config_t initCfg = {
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/* VCORE AVDD18 supplied from iBuck on RD board. */
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.iBuck = true,
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/* CAU_SOC_SLP_REF_CLK is needed for LPOSC. */
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.gateCauRefClk = false,
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};
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POWER_InitPowerConfig(&initCfg);
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}
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#if CONFIG_PM
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static void rdrw61x_pm_state_exit(enum pm_state state)
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{
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switch (state) {
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case PM_STATE_STANDBY:
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rdrw61x_power_init_config();
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break;
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default:
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break;
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}
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}
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#endif
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void board_early_init_hook(void)
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{
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rdrw61x_power_init_config();
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#if CONFIG_PM
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static struct pm_notifier rdrw61x_pm_notifier = {
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.state_exit = rdrw61x_pm_state_exit,
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};
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pm_notifier_register(&rdrw61x_pm_notifier);
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int32_t i;
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/* Set all non-AON pins output low level in sleep mode. */
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for (i = NON_AON_PINS_START; i <= NON_AON_PINS_BREAK; i++) {
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IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
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}
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for (i = NON_AON_PINS_RESTART; i <= NON_AON_PINS_END; i++) {
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IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
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}
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/* Set RF_CNTL 0-3 output low level in sleep mode. */
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for (i = RF_CNTL_PINS_START; i <= RF_CNTL_PINS_END; i++) {
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IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
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}
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#endif
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/*
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* Eventually this code should not be here
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* but should be configured by some SYSCTL node
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*/
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/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm1 */
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SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) |
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SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1);
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/* Select Data in from Transmit I2S - Flexcomm 1 */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(1);
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/* Enable Transmit I2S - Flexcomm 1 for Shared Data Out */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(1);
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/* Set Receive I2S - Flexcomm 0 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[0] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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/* Set Transmit I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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/* Select Receive I2S - Flexcomm 0 Data in from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[0] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
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/* Select Transmit I2S - Flexcomm 1 Data out to shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
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#endif /* CONFIG_I2S_TEST_SEPARATE_DEVICES */
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}
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