d9e4f8fa1d
Initial version of the driver for Infineon CAT1 devices Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
109 lines
2.4 KiB
Text
109 lines
2.4 KiB
Text
/*
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* Copyright (c) 2021 Cypress Semiconductor Corporation.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>
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#include <infineon/psoc6/system_clocks.dtsi>
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#include "cy8cproto_062_4343w-common.dtsi"
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#include "cy8cproto_062_4343w-pinctrl.dtsi"
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/ {
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model = "cy8cproto_062_4343w with an Cypress PSoC™ 6 SoC";
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compatible = "cy8cproto_062_4343w", "PSoC6";
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aliases {
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uart-5 = &uart5;
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i2c-0 = &i2c3;
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watchdog0 = &watchdog0;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart5;
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zephyr,shell-uart = &uart5;
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zephyr,bt_uart = &uart2;
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};
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};
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uart5: &scb5 {
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compatible = "infineon,cat1-uart";
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
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pinctrl-names = "default";
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};
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uart2: &scb2 {
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compatible = "infineon,cat1-uart";
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status = "okay";
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/* The UART bus speed (current_speed) for zephyr_bt_uart should be the same
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* as the default baudrate defined in CYW43xx firmware (default 115200).
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*/
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current-speed = <115200>;
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/* HCI-UART pins*/
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pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx &p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;
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pinctrl-names = "default";
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bt-hci {
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status = "okay";
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compatible = "infineon,cyw43xxx-bt-hci";
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bt-reg-on-gpios = <&gpio_prt3 4 (GPIO_ACTIVE_HIGH)>;
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/* Configuration UART speeds for firmware download (fw-download-speed) and
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* HCI operation (hci-operation-speed).
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* If hci-operation-speed or fw-download-speed are not defined in bt-hci{...}
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* node, cyw43xx driver will use bus/current-speed as default speed.
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*/
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fw-download-speed = <3000000>;
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};
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};
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/* System clock configuration */
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&fll0 {
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status = "okay";
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clock-frequency = <100000000>;
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};
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&clk_hf0 {
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clock-div = <1>;
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clocks = <&fll0>;
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};
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/* CM4 core clock = 100MHz
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* &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
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*/
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&clk_fast {
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clock-div = <1>;
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};
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/* CM0+ core clock = 50MHz
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* &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
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*/
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&clk_slow {
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clock-div = <2>;
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};
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/* PERI core clock = 100MHz
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* &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
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*/
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&clk_peri {
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clock-div = <1>;
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};
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i2c3: &scb3 {
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compatible = "infineon,cat1-i2c";
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/* I2C pins */
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pinctrl-0 = <&p6_0_scb3_i2c_scl &p6_1_scb3_i2c_sda>;
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pinctrl-names = "default";
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};
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&watchdog0 {
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status = "okay";
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};
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