d79d4f0bea
GD32V SoC uses divided clock from core-clock for machine timer clock. Add config of clock divide factor to support GD32V. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
39 lines
1.3 KiB
YAML
39 lines
1.3 KiB
YAML
# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: RISC-V Machine timer
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compatible: "nuclei,machine-timer"
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include: base.yaml
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properties:
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clk-divider:
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type: int
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required: false
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description: |
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clk-divider specifies the division ratio to the CPU frequency that
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clock used by machine timer.
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This property supports the case that the machine timer and CPU use
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different clock sources.
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This configuration is used sometimes for such as low power consumption.
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For example, the CPU clock frequency is 108MHz, and the machine timer
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uses 27MHz, which is the CPU clock divided by 4.
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In this case, the CPU clock frequency is defined in the CPU node
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as follows
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clock-frequency = <108000000>;
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This property takes exponent of the power of 2.
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The relationship with the frequency division ratio is as
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following equation.
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division_ratio = 2^n
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n = log_2(division_ratio)
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Setting clk-divider to 2 specifies the machine timer uses the clock
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that CPU clock frequency divided by (2^2=)4, or 27MHz.
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Devision ratio constants can be found in the
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dt-bindings/timer/nuclei-machine-timer.h header file.
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