d5743e59b2
Add support for the Octavo's OSD32MP1-BRK platform. The board uses Octavo's OSD32MP15x SiP which integrates STM32MP157F MCU and its SoC configuration. Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com> Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
299 lines
9.3 KiB
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299 lines
9.3 KiB
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.. zephyr:board:: osd32mp1_brk
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Overview
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********
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The OSD32MP1-BRK development board by Octavo Systems integrates the OSD32MP15x
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System-in-Package (SiP), which contains a multicore STM32MP157F microprocessor.
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Zephyr OS is ported to run on the Cortex®-M4 core of the STM32MP157F.
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- Common features:
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- OSD32MP15x SiP:
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- STM32MP15x microprocessor:
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- Dual-core Arm® Cortex®-A7 up to 800 MHz, 32 bits
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- Cortex®-M4 up to 209 MHz, 32 bits
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- Embedded SRAM (448 Kbytes) for Cortex®-M4.
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- 512MB DDR3 memory
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- STPMIC1A Power Management
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- Integrated 4kB EEPROM
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- MEMS oscillator
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- Over 100 passive components
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- Small form factor:
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- Dimensions: 75 mm x 46 mm (3 in x 1.8 in)
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- Breadboard-compatible with access to 106 I/Os via two 2x30 100-mil headers
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- Built-in features:
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- μUSB
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- ST-Link header
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- UART
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- μSD card slot
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- 32 kHz crystal
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- User LEDs and reset button
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- 4 Layer Design
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- No Back Side Components
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For a detailed list of features, visit the `OSD32MP1-BRK product page`_.
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Hardware
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********
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The OSD32MP15x SiP in integration with the STM32MP17 SoC provides the following hardware capabilities:
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- Core:
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- 32-bit dual-core Arm® Cortex®-A7
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- L1 32-Kbyte I / 32-Kbyte D for each core
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- 256-Kbyte unified level 2 cache
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- Arm® NEON™ and Arm® TrustZone®
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- 32-bit Arm® Cortex®-M4 with FPU/MPU
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- Up to 209 MHz (Up to 703 CoreMark®)
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- Memories:
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- 512 MB DDR3L memory (on SiP)
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- 708 Kbytes of internal SRAM:
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- 256 KB AXI SYSRAM
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- 384 KB AHB SRAM
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- 64 KB AHB SRAM in backup domain
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- Dual mode Quad-SPI memory interface
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- Flexible external memory controller with up to 16-bit data bus
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- Integrated 4 KB EEPROM (on SiP)
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- Security/safety:
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- Secure boot, TrustZone® peripherals with Cortex®-M4 resource isolation
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- Clock management:
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- Internal oscillators:
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- 64 MHz HSI oscillator
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- 4 MHz CSI oscillator
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- 32 kHz LSI oscillator
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- External oscillators:
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- 8-48 MHz HSE oscillator
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- 32.768 kHz LSE oscillator
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- 6 × PLLs with fractional mode
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- MEMS oscillator (on SiP)
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- General-purpose input/outputs:
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- Up to 176 I/O ports with interrupt capability
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- 106 I/Os routed to expansion headers (on board)
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- Interconnect matrix
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- 3 DMA controllers
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- Communication peripherals:
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- 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
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- 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
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- 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
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- 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
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- SPDIF Rx with 4 inputs
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- HDMI-CEC interface
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- MDIO Slave interface
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- 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
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- 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
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- 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
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- 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
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- 8- to 14-bit camera interface up to 140 Mbyte/s
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- 6 analog peripherals
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- 2 × ADCs with 16-bit max. resolution
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- 1 × temperature sensor
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- 2 × 12-bit D/A converters (1 MHz)
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- 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
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filters
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- Internal or external ADC/DAC reference VREF+
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- Graphics:
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- 3D GPU: Vivante® - OpenGL® ES 2.0
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- LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
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- MIPI® DSI 2 data lanes up to 1 GHz each
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- Timers:
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- 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
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(incremental) encoder input
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- 2 × 16-bit advanced motor control timers
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- 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
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- 5 × 16-bit low-power timers
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- RTC with sub-second accuracy and hardware calendar
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- 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
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- 1 × SysTick Cortex®-M4 timer
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- Hardware acceleration:
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- AES 128, 192, 256, TDES
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- HASH (MD5, SHA-1, SHA224, SHA256), HMAC
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- 2 × true random number generator (3 oscillators each)
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- 2 × CRC calculation unit
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- Debug mode:
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- Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
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- 8-Kbyte embedded trace buffer
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- 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
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More information about the hardware can be found here:
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- `STM32MP157F on www.st.com`_
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- `OSD32MP15x SiP documentation`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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OSD32MP1-BRK Board schematic is available here:
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`OSD32MP1-BRK schematics`_.
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OSD32MP1-BRK Board pin mapping is available here:
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`OSD32MP1-BRK default pin mapping`_.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- UART7 TX/RX: PA15/PB3 (default console)
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- I2C5 SCL/SDA: PA11/PA12
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- SPI4 SCK/MISO/MOSI: PE12/PE13/PE14
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System Clock
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------------
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The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.
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This value must match the configured mlhclk_ck frequency.
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Serial Port
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-----------
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The Zephyr console output is assigned by default to the RAM console to be dumped
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by the Linux Remoteproc Framework on Cortex®-A7 core. To enable the USART2 console, modify
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the board's devicetree and the osd32mp1_brk_defconfig board file (or prj.conf project files)
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Default USART settings are 115200 8N1.
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Programming and Debugging
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*************************
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The STM32MP157F doesn't have QSPI flash for Cortex®-M4 and it needs to be
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started by the Cortex®-A7 core. The Cortex®-A7 core is responsible for loading the
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Cortex®-M4 binary application into the RAM, and getting Cortex®-M4 out of reset.
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Cortex®-A7 can perform these steps at bootloader level or after the Linux
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system has booted.
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Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
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the 0x00000000 (RETRAM) address, and the vector table should be loaded at this address.
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The following table provides memory mappings for Cortex®-A7 and Cortex®-M4:
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+------------+-----------------------+------------------------+----------------+
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| Region | Cortex®-A7 | Cortex®-M4 | Size |
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+============+=======================+========================+================+
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| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB |
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+------------+-----------------------+------------------------+----------------+
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| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB |
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+------------+-----------------------+------------------------+----------------+
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| DDR | 0xC0000000-0x20000000 | | 512MB |
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+------------+-----------------------+------------------------+----------------+
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Refer to following instructions to boot Zephyr on the Cortex®-M4 core:
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1. Download and install the Octavo OpenSTLinux distribution:
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`OSD32MP1 OpenSTLinux`_.
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(You can find more details about this process here: `OSD32MP1-BRK Getting Started`_)
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2. Build the Zephyr application:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: osd32mp1_brk
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:goals: build
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3. Transfer the built firmware to the board via USB RNDIS:
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.. code-block:: console
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scp build/zephyr/zephyr.elf root@192.168.7.1:/lib/firmware
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4. Boot Zephyr on the Cortex®-M4 core:
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.. code-block:: console
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ssh root@192.168.7.1
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echo stop > /sys/class/remoteproc/remoteproc0/state
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echo -n zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware
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echo start > /sys/class/remoteproc/remoteproc0/state
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cat /sys/kernel/debug/remoteproc/remoteproc0/trace0
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The console output should display:
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.. code-block::
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*** Booting Zephyr OS build v4.0.0 ***
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Hello World! osd32mp1_brk/osd32mp15x
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Refer to `OSD32MP1-BRK Getting Started`_ and `stm32mp157 boot Cortex-M4 firmware`_ wiki page for more
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detailed instructions.
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Debugging
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=========
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You can debug an application using OpenOCD and GDB. The solution proposed below
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is based on attaching to preloaded firmware, which is available only for a Linux
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environment. The firmware must first be loaded by the Cortex®-A7. The developer
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then attaches the debugger to the running Zephyr using OpenOCD.
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The principle is to attach to the firmware already loaded by Linux.
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- Build the sample:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: osd32mp1_brk
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:goals: build
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- Copy the firmware on the target filesystem, load it and start it (`stm32mp157 boot Cortex-M4 firmware`_).
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- Attach to the target:
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.. code-block:: console
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west attach
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.. _OSD32MP1-BRK product page:
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https://octavosystems.com/octavo_products/osd32mp1-brk/
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.. _OSD32MP1-BRK documentation:
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https://octavosystems.com/docs/osd32mp15x-datasheet/
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.. _STM32MP157F on www.st.com:
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https://www.st.com/en/microcontrollers-microprocessors/stm32mp157f.html
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.. _OSD32MP15x SiP documentation:
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https://octavosystems.com/docs/osd32mp15x-datasheet/
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.. _OSD32MP1 OpenSTLinux:
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https://octavosystems.com/files/osd32mp1-brk-openstlinux-v3-0/
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.. _OSD32MP1-BRK Getting Started:
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https://octavosystems.com/app_notes/osd32mp1-brk-getting-started/
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.. _stm32mp157 boot Cortex-M4 firmware:
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https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework
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.. _OSD32MP1-BRK schematics:
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https://octavosystems.com/docs/osd32mp1-brk-schematics/
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.. _OSD32MP1-BRK default pin mapping:
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https://octavosystems.com/octavosystems.com/wp-content/uploads/2020/05/Default-Pin-Mapping.pdf
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