d4c0fda714
Configure STM32 RTC for a large selction of boards. Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
175 lines
3.8 KiB
Text
175 lines
3.8 KiB
Text
/*
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* Copyright (c) 2023-2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/h7/stm32h750Xb.dtsi>
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#include <st/h7/stm32h750xbhx-pinctrl.dtsi>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "STMicroelectronics STM32H750B DISCOVERY KIT";
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compatible = "st,stm32h750b-dk";
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chosen {
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zephyr,console = &usart3;
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zephyr,shell-uart = &usart3;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,flash-controller = &mt25ql512ab1;
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};
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sdram2: sdram@d0000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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device_type = "memory";
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reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
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zephyr,memory-region = "SDRAM2";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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leds {
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compatible = "gpio-leds";
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red_led: led_1 {
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gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
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label = "USER1 LD6";
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};
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green_led: led_2 {
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gpios = <&gpioj 2 GPIO_ACTIVE_LOW>;
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label = "USER2 LD7";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button: button {
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label = "User";
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gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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aliases {
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led0 = &green_led;
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led1 = &red_led;
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sw0 = &user_button;
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spi-flash0 = &mt25ql512ab1;
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};
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(25)>;
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hse-bypass;
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status = "okay";
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};
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&clk_lse {
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status = "okay";
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};
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&pll {
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div-m = <5>;
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mul-n = <192>;
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div-p = <2>;
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div-q = <4>;
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div-r = <4>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(480)>;
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d1cpre = <1>;
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hpre = <2>;
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d1ppre = <2>;
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d2ppre1 = <2>;
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d2ppre2 = <2>;
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d3ppre = <2>;
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};
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&usart3 {
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pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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&quadspi {
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pinctrl-names = "default";
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pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
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&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
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&quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
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&quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
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&quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
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flash-id = <1>;
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status = "okay";
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mt25ql512ab1: qspi-nor-flash-1@90000000 {
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compatible = "st,stm32-qspi-nor";
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reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
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qspi-max-frequency = <72000000>;
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spi-bus-width = <4>;
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 DT_SIZE_M(64)>;
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};
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};
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};
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mt25ql512ab2: qspi-nor-flash-2@90000000 {
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compatible = "st,stm32-qspi-nor";
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reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
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qspi-max-frequency = <72000000>;
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status = "okay";
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};
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};
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&fmc {
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pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
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&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
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&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
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&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
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&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
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&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
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&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
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&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
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&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
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&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
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&fmc_d15_pd10>;
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pinctrl-names = "default";
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status = "okay";
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sdram {
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status = "okay";
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power-up-delay = <100>;
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num-auto-refresh = <8>;
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mode-register = <0x220>;
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refresh-rate = <0x603>;
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bank@1 {
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reg = <1>;
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st,sdram-control = <STM32_FMC_SDRAM_NC_8
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STM32_FMC_SDRAM_NR_12
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STM32_FMC_SDRAM_MWID_16
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STM32_FMC_SDRAM_NB_4
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STM32_FMC_SDRAM_CAS_3
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STM32_FMC_SDRAM_SDCLK_PERIOD_2
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STM32_FMC_SDRAM_RBURST_ENABLE
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STM32_FMC_SDRAM_RPIPE_0>;
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st,sdram-timing = <2 7 4 7 2 2 2>;
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};
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};
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};
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&rtc {
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
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<&rcc STM32_SRC_LSE RTC_SEL(1)>;
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status = "okay";
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};
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