a87a6d82ac
The DTS changes introduced in 7ae220c845
changes the naming of GPIO related macros. This updates the usage
of previous macros via DTS fixup.
Fixes #10993
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
/*
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* Copyright (c) 2018, Intel Corporation
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* Copyright (c) 2011-2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for the Apollo Lake SoC
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*
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* This module provides routines to initialize and support soc-level hardware
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* for the Apollo Lake SoC.
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*/
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#include <kernel.h>
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#include "soc.h"
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#include <uart.h>
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#include <device.h>
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#include <init.h>
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#ifdef CONFIG_X86_MMU
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/* loapic */
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MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
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/* ioapic */
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MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif /* CONFIG_HPET_TIMER */
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/* for UARTs */
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#ifdef CONFIG_UART_NS16550
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#ifdef CONFIG_UART_NS16550_PORT_0
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_1
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_2
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_3
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_3_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#endif /* CONFIG_UART_NS16550 */
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/* for I2C controllers */
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#ifdef CONFIG_I2C
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#ifdef CONFIG_I2C_0
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MMU_BOOT_REGION(CONFIG_I2C_0_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_1
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MMU_BOOT_REGION(CONFIG_I2C_1_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_2
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MMU_BOOT_REGION(CONFIG_I2C_2_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_3
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MMU_BOOT_REGION(CONFIG_I2C_3_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_4
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MMU_BOOT_REGION(CONFIG_I2C_4_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_5
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MMU_BOOT_REGION(CONFIG_I2C_5_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_6
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MMU_BOOT_REGION(CONFIG_I2C_6_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_7
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MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#endif /* CONFIG_I2C */
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/* for GPIO controller */
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#ifdef CONFIG_GPIO_INTEL_APL
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0,
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CONFIG_APL_GPIO_MEM_SIZE_0,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1,
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CONFIG_APL_GPIO_MEM_SIZE_1,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2,
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CONFIG_APL_GPIO_MEM_SIZE_2,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3,
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CONFIG_APL_GPIO_MEM_SIZE_3,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#endif /* CONFIG_X86_MMU */
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