Andy Ross a230fafde5 arch/xtensa: soc/intel_adsp: Rework MP code entry ... Instead of passing the crt1 _start function as the entry code for auxiliary CPUs, use a tiny assembly stub instead which can avoid the runtime testing needed to skip the work in _start. All the crt1 code was doing was clearing BSS (which must not happen on a second CPU) and setting the stack pointer (which is wrong on the second CPU). This allows us to clean out the SMP code in crt1. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-03-08 11:14:27 -05:00
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esp32	esp32: drivers: spi_flash: add host flash support	2021-03-06 09:34:35 -05:00
intel_adsp	arch/xtensa: soc/intel_adsp: Rework MP code entry	2021-03-08 11:14:27 -05:00
intel_s1000	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
sample_controller	xtensa: set toolchain variant per SoC	2020-12-20 14:30:50 -05:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00