cea0b3a9c2
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
75 lines
2 KiB
C
75 lines
2 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include "soc.h"
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <xtensa/config/core-isa.h>
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#include <xtensa/corebits.h>
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#include <kernel_structs.h>
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#include <string.h>
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#include <toolchain/gcc.h>
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#include <zephyr/types.h>
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extern void _Cstart(void);
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/*
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* This is written in C rather than assembly since, during the port bring up,
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* Zephyr is being booted by the Espressif bootloader. With it, the C stack
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* is already set up.
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*/
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void __attribute__((section(".iram1"))) __start(void)
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{
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volatile u32_t *wdt_rtc_reg = (u32_t *)RTC_CNTL_WDTCONFIG0_REG;
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volatile u32_t *wdt_timg_reg = (u32_t *)TIMG_WDTCONFIG0_REG(0);
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volatile u32_t *app_cpu_config_reg = (u32_t *)DPORT_APPCPU_CTRL_B_REG;
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extern u32_t _init_start;
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extern u32_t _bss_start;
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extern u32_t _bss_end;
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/* Move the exception vector table to IRAM. */
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__asm__ __volatile__ (
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"wsr %0, vecbase"
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:
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: "r"(&_init_start));
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/* Zero out BSS. Clobber _bss_start to avoid memset() elision. */
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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__asm__ __volatile__ (
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""
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:
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: "g"(&_bss_start)
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: "memory");
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/* The watchdog timer is enabled in the bootloader. We're done booting,
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* so disable it.
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*/
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*wdt_rtc_reg &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
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*wdt_timg_reg &= ~TIMG_WDT_FLASHBOOT_MOD_EN;
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/* Disable normal interrupts. */
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__asm__ __volatile__ (
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"wsr %0, PS"
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:
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: "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
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/* Disable CPU1 while we figure out how to have SMP in Zephyr. */
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*app_cpu_config_reg &= ~DPORT_APPCPU_CLKGATE_EN;
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/* Initialize the architecture CPU pointer. Some of the
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* initialization code wants a valid _current before
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* kernel_arch_init() is invoked.
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*/
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
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/* Start Zephyr */
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_Cstart();
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CODE_UNREACHABLE;
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}
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