c91a70e130
The STM32u% series of processors has a unique set of clock sources for the FDCAN peripheral. This brings the selection in line with the existing can_stm32fd clock selection Kconfigs. This change was tested on a proprietary board using the STM32U5 series which exposes the CAN pins of the SOC using a transciever on a live CAN bus as well as on the nucleo_g474re board from ST in loopback mode. HSE and PLL1Q tests run and all passed. PLL2P is not currently supported by the clock drivers for STM32U5, and as such is currently untested. When this support is added, the driver should be able to use this clock without issue. When changes from #42097 are merged this fix should be deprecated in favor of using the methods outlined there. Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
80 lines
1.8 KiB
Text
80 lines
1.8 KiB
Text
# STM32 CAN configuration options
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# Copyright (c) 2020 Alexander Wachter
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_STM32_FDCAN := st,stm32-fdcan
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config CAN_STM32FD
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bool "STM32 FDCAN driver"
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default $(dt_compat_enabled,$(DT_COMPAT_STM32_FDCAN))
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select CAN_MCAN
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select USE_STM32_LL_RCC
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if CAN_STM32FD
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config CAN_MAX_STD_ID_FILTER
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int "Maximum number of std ID filters"
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default 28
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range 0 28
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help
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Defines the maximum number of filters with standard ID (11-bit)
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that can be attached.
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config CAN_MAX_EXT_ID_FILTER
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int "Maximum number of ext ID filters"
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default 8
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range 0 8
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help
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Defines the maximum number of filters with extended ID (29-bit)
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that can be attached.
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choice CAN_STM32FD_CLOCK_SOURCE
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prompt "CAN clock source"
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default CAN_STM32FD_CLOCK_SOURCE_HSE
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help
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CAN clock source selection.
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config CAN_STM32FD_CLOCK_SOURCE_HSE
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bool "HSE"
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help
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HSE clock used as FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PLL
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bool "PLL"
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depends on !SOC_SERIES_STM32U5X
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help
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PLL "Q" clock used ad FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PCLK1
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bool "PCLK1"
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depends on !SOC_SERIES_STM32U5X
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help
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PCLK1 clock used ad FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PLL1Q
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bool "PLL1Q"
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depends on SOC_SERIES_STM32U5X
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help
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PLL1 "Q" clock used as FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PLL2P
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bool "PLL2P"
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depends on SOC_SERIES_STM32U5X
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help
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PLL2 "P" clock used as FDCAN clock source.
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endchoice
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config CAN_STM32FD_CLOCK_DIVISOR
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int "CAN clock divisor"
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depends on CAN_STM32FD_CLOCK_SOURCE_PCLK1
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range 1 30
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default 1
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help
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The APB clock is divided by this value (stored in CKDIV register)
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before it is fed to the CAN core.
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Note that the the divisor affects all CAN controllers.
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Allowed values: 1 or 2 * n, where n <= 15.
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endif # CAN_STM32FD
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