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zephyr/soc
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Henrik Brix Andersen 9d51d9145b soc: arm: xilinx: zynq7000: default to 1 CPU core 
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
..
arc soc: arch: snps_arc_iot: select UART_NS16550_ACCESS_IOPORT 2022-06-16 11:28:13 +02:00
arm soc: arm: xilinx: zynq7000: default to 1 CPU core 2022-06-28 20:46:11 +02:00
arm64 soc: qemu_cortex_a53: remove pl011 entry from mmu_regions array 2022-06-07 11:54:13 +02:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
riscv soc: riscv: telink_b91: add dfu related configurations for b91 platform 2022-06-24 20:25:33 +02:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 test: Enable the GPIO tests on EHL_CRB. 2022-06-21 10:47:56 +02:00
xtensa soc/xtensa/intel_adsp/tools: Do not use grep Perl extensions 2022-06-27 15:41:00 -05:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00