83f733ce59
The fatal log now contains - Trap type in human readable representation - Integer registers visible to the program when trap was taken - Special register values such as PC and PSR - Backtrace with PC and SP If CONFIG_EXTRA_EXCEPTION_INFO is enabled, then all the above is logged. If not, only the special registers are logged. The format is inspired by the GRMON debug monitor and TSIM simulator. A quick guide on how to use the values is in fatal.c. It now looks like this: E: tt = 0x02, illegal_instruction E: E: INS LOCALS OUTS GLOBALS E: 0: 00000000 f3900fc0 40007c50 00000000 E: 1: 00000000 40004bf0 40008d30 40008c00 E: 2: 00000000 40004bf4 40008000 00000003 E: 3: 40009158 00000000 40009000 00000002 E: 4: 40008fa8 40003c00 40008fa8 00000008 E: 5: 40009000 f3400fc0 00000000 00000080 E: 6: 4000a1f8 40000050 4000a190 00000000 E: 7: 40002308 00000000 40001fb8 000000c1 E: E: psr: f30000c7 wim: 00000008 tbr: 40000020 y: 00000000 E: pc: 4000a1f4 npc: 4000a1f8 E: E: pc sp E: #0 4000a1f4 4000a190 E: #1 40002308 4000a1f8 E: #2 40003b24 4000a258 Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
136 lines
2.8 KiB
C
136 lines
2.8 KiB
C
/*
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* Copyright (c) 2019-2020 Cobham Gaisler AB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief SPARC specific kernel interface header
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* This header contains the SPARC specific kernel interface. It is
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* included by the generic kernel interface header (arch/cpu.h)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_SPARC_ARCH_H_
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#define ZEPHYR_INCLUDE_ARCH_SPARC_ARCH_H_
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#include <arch/sparc/thread.h>
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#include <arch/sparc/sparc.h>
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#include <arch/common/sys_bitops.h>
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#include <arch/common/sys_io.h>
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#include <arch/common/ffs.h>
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <soc.h>
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#include <devicetree.h>
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/* stacks, for SPARC architecture stack shall be 8byte-aligned */
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#define ARCH_STACK_PTR_ALIGN 8
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/*
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* Software trap numbers.
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* Assembly usage: "ta SPARC_SW_TRAP_<TYPE>"
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*/
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#define SPARC_SW_TRAP_FLUSH_WINDOWS 0x03
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#define SPARC_SW_TRAP_SET_PIL 0x09
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#define SPARC_SW_TRAP_EXCEPT 0x0F
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#ifndef _ASMLANGUAGE
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#include <sys/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STACK_ROUND_UP(x) ROUND_UP(x, ARCH_STACK_PTR_ALIGN)
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/*
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* SOC specific function to translate from processor interrupt request level
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* (1..15) to logical interrupt source number. For example by probing the
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* interrupt controller.
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*/
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int z_sparc_int_get_source(int irl);
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void z_irq_spurious(const void *unused);
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#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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{ \
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Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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}
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static ALWAYS_INLINE unsigned int z_sparc_set_pil_inline(unsigned int newpil)
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{
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register uint32_t oldpil __asm__ ("o0") = newpil;
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__asm__ volatile (
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"ta %1\nnop\n" :
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"=r" (oldpil) :
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"i" (SPARC_SW_TRAP_SET_PIL), "r" (oldpil) :
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"memory"
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);
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return oldpil;
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}
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static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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return z_sparc_set_pil_inline(15);
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}
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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z_sparc_set_pil_inline(key);
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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return key == 0;
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}
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static ALWAYS_INLINE void arch_nop(void)
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{
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__asm__ volatile ("nop");
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}
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extern uint32_t sys_clock_cycle_get_32(void);
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static inline uint32_t arch_k_cycle_get_32(void)
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{
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return sys_clock_cycle_get_32();
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}
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struct __esf {
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uint32_t out[8];
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uint32_t global[8];
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uint32_t psr;
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uint32_t pc;
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uint32_t npc;
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uint32_t wim;
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uint32_t tbr;
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uint32_t y;
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};
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typedef struct __esf z_arch_esf_t;
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#define ARCH_EXCEPT(reason_p) \
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do { \
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register uint32_t _g1 __asm__("g1") = reason_p; \
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\
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__asm__ volatile ( \
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"ta %[vector]\n\t" \
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: \
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: [vector] "i" (SPARC_SW_TRAP_EXCEPT), "r" (_g1) \
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: "memory" \
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); \
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CODE_UNREACHABLE; \
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} while (false)
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#ifdef __cplusplus
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}
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#endif
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#endif /*_ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_ARCH_H_ */
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