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zephyr/soc/arm/st_stm32/stm32f4/dts_fixup.h
Erwan Gouriou c4de0d3b5b drivers: gpio: Use new DT macros for device driver init 
Kconfig based device declaration is kept as is.
Clean up the fixup files.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-04-02 06:50:05 -05:00

213 lines
11 KiB
C
Raw Blame History

/* SPDX-License-Identifier: Apache-2.0 */
/* SoC level DTS fixup file */
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_NAME DT_ST_STM32_I2C_V1_40005400_LABEL
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_NAME DT_ST_STM32_I2C_V1_40005800_LABEL
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_NAME DT_ST_STM32_I2C_V1_40005C00_LABEL
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS
#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY
#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL
#define DT_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0
#define DT_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS
#define DT_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS
#define DT_I2S_1_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_CONTROLLER
#define DT_I2S_1_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL
#define DT_I2S_1_DMA_SLOT_TX DT_ST_STM32_I2S_40013000_TX_DMAS_SLOT
#define DT_I2S_1_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_1_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_FEATURES
#define DT_I2S_1_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_CONTROLLER
#define DT_I2S_1_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL
#define DT_I2S_1_DMA_SLOT_RX DT_ST_STM32_I2S_40013000_RX_DMAS_SLOT
#define DT_I2S_1_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_1_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_FEATURES
#define DT_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS
#define DT_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY
#define DT_I2S_2_NAME DT_ST_STM32_I2S_40003800_LABEL
#define DT_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0
#define DT_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS
#define DT_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS
#define DT_I2S_2_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_CONTROLLER
#define DT_I2S_2_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL
#define DT_I2S_2_DMA_SLOT_TX DT_ST_STM32_I2S_40003800_TX_DMAS_SLOT
#define DT_I2S_2_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_2_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_FEATURES
#define DT_I2S_2_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_CONTROLLER
#define DT_I2S_2_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL
#define DT_I2S_2_DMA_SLOT_RX DT_ST_STM32_I2S_40003800_RX_DMAS_SLOT
#define DT_I2S_2_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_2_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_FEATURES
#define DT_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS
#define DT_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY
#define DT_I2S_3_NAME DT_ST_STM32_I2S_40003C00_LABEL
#define DT_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0
#define DT_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS
#define DT_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS
#define DT_I2S_3_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_CONTROLLER
#define DT_I2S_3_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL
#define DT_I2S_3_DMA_SLOT_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_SLOT
#define DT_I2S_3_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_3_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_FEATURES
#define DT_I2S_3_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_CONTROLLER
#define DT_I2S_3_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL
#define DT_I2S_3_DMA_SLOT_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_SLOT
#define DT_I2S_3_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_3_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_FEATURES
#define DT_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS
#define DT_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY
#define DT_I2S_4_NAME DT_ST_STM32_I2S_40013400_LABEL
#define DT_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0
#define DT_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS
#define DT_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS
#define DT_I2S_4_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_CONTROLLER
#define DT_I2S_4_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL
#define DT_I2S_4_DMA_SLOT_TX DT_ST_STM32_I2S_40013400_TX_DMAS_SLOT
#define DT_I2S_4_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_4_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_FEATURES
#define DT_I2S_4_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_CONTROLLER
#define DT_I2S_4_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL
#define DT_I2S_4_DMA_SLOT_RX DT_ST_STM32_I2S_40013400_RX_DMAS_SLOT
#define DT_I2S_4_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_4_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_FEATURES
#define DT_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS
#define DT_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY
#define DT_I2S_5_NAME DT_ST_STM32_I2S_40015000_LABEL
#define DT_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0
#define DT_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS
#define DT_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS
#define DT_I2S_5_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_CONTROLLER
#define DT_I2S_5_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL
#define DT_I2S_5_DMA_SLOT_TX DT_ST_STM32_I2S_40015000_TX_DMAS_SLOT
#define DT_I2S_5_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_5_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_FEATURES
#define DT_I2S_5_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_CONTROLLER
#define DT_I2S_5_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL
#define DT_I2S_5_DMA_SLOT_RX DT_ST_STM32_I2S_40015000_RX_DMAS_SLOT
#define DT_I2S_5_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_5_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_FEATURES
#define DT_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS
#define DT_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY
#define DT_I2S_6_NAME DT_ST_STM32_I2S_40015400_LABEL
#define DT_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0
#define DT_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS
#define DT_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS
#define DT_I2S_6_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_CONTROLLER
#define DT_I2S_6_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL
#define DT_I2S_6_DMA_SLOT_TX DT_ST_STM32_I2S_40015400_TX_DMAS_SLOT
#define DT_I2S_6_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_6_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_FEATURES
#define DT_I2S_6_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_CONTROLLER
#define DT_I2S_6_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL
#define DT_I2S_6_DMA_SLOT_RX DT_ST_STM32_I2S_40015400_RX_DMAS_SLOT
#define DT_I2S_6_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_6_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_FEATURES
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX
#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0
#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1
#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE
#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW
#define DT_CAN_1_PROP_SEG DT_ST_STM32_CAN_40006400_PROP_SEG
#define DT_CAN_1_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PHASE_SEG1
#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2
#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
#define DT_CAN_2_BASE_ADDRESS DT_ST_STM32_CAN_40006800_BASE_ADDRESS
#define DT_CAN_2_BUS_SPEED DT_ST_STM32_CAN_40006800_BUS_SPEED
#define DT_CAN_2_NAME DT_ST_STM32_CAN_40006800_LABEL
#define DT_CAN_2_IRQ_TX DT_ST_STM32_CAN_40006800_IRQ_TX
#define DT_CAN_2_IRQ_RX0 DT_ST_STM32_CAN_40006800_IRQ_RX0
#define DT_CAN_2_IRQ_RX1 DT_ST_STM32_CAN_40006800_IRQ_RX1
#define DT_CAN_2_IRQ_SCE DT_ST_STM32_CAN_40006800_IRQ_SCE
#define DT_CAN_2_IRQ_PRIORITY DT_ST_STM32_CAN_40006800_IRQ_0_PRIORITY
#define DT_CAN_2_SJW DT_ST_STM32_CAN_40006800_SJW
#define DT_CAN_2_PROP_SEG DT_ST_STM32_CAN_40006800_PROP_SEG
#define DT_CAN_2_PHASE_SEG1 DT_ST_STM32_CAN_40006800_PHASE_SEG1
#define DT_CAN_2_PHASE_SEG2 DT_ST_STM32_CAN_40006800_PHASE_SEG2
#define DT_CAN_2_CLOCK_BUS DT_ST_STM32_CAN_40006800_CLOCK_BUS
#define DT_CAN_2_CLOCK_BITS DT_ST_STM32_CAN_40006800_CLOCK_BITS
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f4_flash_controller))
/* End of SoC Level DTS fixup file */
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