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Eric Ackermann e367e1d607 soc: cva6: Add device tree node for RISC-V mtimer 
The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-04-18 17:46:30 +02:00
..
andes drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
efinix drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
espressif drivers: uart: espressif: Add LP UART driver 2025-04-11 13:34:17 +02:00
gd driver: interrupt_controller: intc_clic: rework to standard CLIC driver 2025-04-04 14:55:50 +02:00
ite drivers/watchdog/it51xxx: implement watchdog driver 2025-04-15 09:28:19 +02:00
lowrisc drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
microchip drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
niosv drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
nordic dts: nordic: nrf54: Add nRF54L09 FLPR 2025-03-28 08:34:23 +01:00
openhwgroup soc: cva6: Add device tree node for RISC-V mtimer 2025-04-18 17:46:30 +02:00
openisa soc/openisa: enable the C extension 2024-07-03 15:06:14 -04:00
qemu drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
sensry dts: sy1xx: add support for i2c 2025-03-14 14:39:55 +01:00
sifive drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
starfive drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
telink drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
wch dts: riscv: wch: added i2c node 2025-04-17 21:17:06 +02:00
neorv32.dtsi dts: bindings: neorv32: use vendor prefix 2025-03-11 05:36:35 +01:00
renode_riscv32_virt.dtsi drivers: timer: Harmonize mtime-based RISC-V timers 2025-01-22 05:39:59 +01:00
riscv32-litex-vexriscv.dtsi boards: litex: vexriscv: add litei2c controller 2025-03-27 14:01:11 +01:00