c0e3ec7f08
Instead of waiting forever and potentially allowing infinite loop on ISR, wait some arbitrary amount of cycles to error out if it isn't happening. Still make this configurable for debugging purposes. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
52 lines
1.9 KiB
Text
52 lines
1.9 KiB
Text
# Copyright 2018, 2024-2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SPI_MCUX_LPSPI
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bool "NXP LPSPI peripheral"
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default y
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depends on DT_HAS_NXP_LPSPI_ENABLED
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depends on CLOCK_CONTROL
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select PINCTRL
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help
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Enable driver support for NXP LPSPI.
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if SPI_MCUX_LPSPI
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config SPI_MCUX_LPSPI_DMA
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bool "NXP LPSPI DMA-based Driver"
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default y
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select DMA
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depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas)
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help
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Enable DMA-based transfers for LPSPI peripherals
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that have a dmas property specified in their DT node.
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The DMA based driver prioritizes bandwidth over latency, due to
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DMA being more efficient for larger data transfers, to avoid CPU
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having to be utilized to do the work. However, setting up a DMA
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transfer is more complicated setup than just starting the transfer
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immediately with CPU, so there could be more latency between
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the point of requesting a transfer and when it actually starts.
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config SPI_MCUX_LPSPI_CPU
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bool "NXP LPSPI CPU-based driver"
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default y
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depends on $(dt_compat_any_not_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas) || !SPI_MCUX_LPSPI_DMA
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help
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Enable "normal" CPU based SPI driver for LPSPI.
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This has lower latency than DMA-based driver but over the
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longer transfers will likely have less bandwidth and use more CPU time.
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config SPI_NXP_LPSPI_TXFIFO_WAIT_CYCLES
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int "Number of CPU cycles to wait on TX fifo empty"
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default 0 if DEBUG
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default 10000
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help
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This option most likely does not need changed.
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The drivers tend to need to wait on confirming the transmit command
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is consumed by the hardware by checking of the TX fifo is emptied.
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This option gives a maximum number of CPU cycles to wait on that check.
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The special value of 0 means infinite, which can be useful for debugging
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for if there is some programming error that causes TX fifo not to empty.
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The default of 10000 is arbitrary.
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endif # SPI_MCUX_LPSPI
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