be387aa1c2
This update Atmel sam and sam0 ethernet gmac and mdio drivers to use pinctrl driver and API. It updates all boards with new pinctrl groups format. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
151 lines
3.6 KiB
C
151 lines
3.6 KiB
C
/*
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* Copyright (c) 2021 IP-Logix Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_mdio
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#include <errno.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/mdio.h>
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#include <drivers/pinctrl.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(mdio_sam, CONFIG_MDIO_LOG_LEVEL);
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/* GMAC */
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#ifdef CONFIG_SOC_FAMILY_SAM0
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#define GMAC_MAN MAN.reg
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#define GMAC_NSR NSR.reg
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#define GMAC_NCR NCR.reg
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#endif
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struct mdio_sam_dev_data {
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struct k_sem sem;
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};
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struct mdio_sam_dev_config {
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Gmac * const regs;
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const struct pinctrl_dev_config *pcfg;
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int protocol;
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};
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static int mdio_transfer(const struct device *dev, uint8_t prtad, uint8_t devad,
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uint8_t rw, uint16_t data_in, uint16_t *data_out)
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{
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const struct mdio_sam_dev_config *const cfg = dev->config;
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struct mdio_sam_dev_data *const data = dev->data;
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int timeout = 50;
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k_sem_take(&data->sem, K_FOREVER);
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/* Write mdio transaction */
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if (cfg->protocol == CLAUSE_45) {
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cfg->regs->GMAC_MAN = (GMAC_MAN_OP(rw ? 0x2 : 0x3))
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| GMAC_MAN_WTN(0x02)
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| GMAC_MAN_PHYA(prtad)
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| GMAC_MAN_REGA(devad)
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| GMAC_MAN_DATA(data_in);
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} else if (cfg->protocol == CLAUSE_22) {
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cfg->regs->GMAC_MAN = GMAC_MAN_CLTTO
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| (GMAC_MAN_OP(rw ? 0x2 : 0x1))
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| GMAC_MAN_WTN(0x02)
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| GMAC_MAN_PHYA(prtad)
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| GMAC_MAN_REGA(devad)
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| GMAC_MAN_DATA(data_in);
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} else {
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LOG_ERR("Unsupported protocol");
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}
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/* Wait until done */
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while (!(cfg->regs->GMAC_NSR & GMAC_NSR_IDLE)) {
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if (timeout-- == 0U) {
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LOG_ERR("transfer timedout %s", dev->name);
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k_sem_give(&data->sem);
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return -ETIMEDOUT;
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}
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k_sleep(K_MSEC(5));
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}
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if (data_out) {
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*data_out = cfg->regs->GMAC_MAN & GMAC_MAN_DATA_Msk;
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}
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k_sem_give(&data->sem);
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return 0;
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}
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static int mdio_sam_read(const struct device *dev, uint8_t prtad, uint8_t devad,
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uint16_t *data)
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{
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return mdio_transfer(dev, prtad, devad, 1, 0, data);
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}
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static int mdio_sam_write(const struct device *dev, uint8_t prtad,
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uint8_t devad, uint16_t data)
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{
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return mdio_transfer(dev, prtad, devad, 0, data, NULL);
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}
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static void mdio_sam_bus_enable(const struct device *dev)
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{
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const struct mdio_sam_dev_config *const cfg = dev->config;
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cfg->regs->GMAC_NCR |= GMAC_NCR_MPE;
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}
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static void mdio_sam_bus_disable(const struct device *dev)
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{
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const struct mdio_sam_dev_config *const cfg = dev->config;
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cfg->regs->GMAC_NCR &= ~GMAC_NCR_MPE;
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}
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static int mdio_sam_initialize(const struct device *dev)
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{
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const struct mdio_sam_dev_config *const cfg = dev->config;
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struct mdio_sam_dev_data *const data = dev->data;
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int retval;
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k_sem_init(&data->sem, 1, 1);
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retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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return retval;
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}
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static const struct mdio_driver_api mdio_sam_driver_api = {
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.read = mdio_sam_read,
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.write = mdio_sam_write,
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.bus_enable = mdio_sam_bus_enable,
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.bus_disable = mdio_sam_bus_disable,
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};
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#define MDIO_SAM_CONFIG(n) \
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static const struct mdio_sam_dev_config mdio_sam_dev_config_##n = { \
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.regs = (Gmac *)DT_REG_ADDR(DT_INST_PARENT(n)), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.protocol = DT_INST_ENUM_IDX(n, protocol), \
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};
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#define MDIO_SAM_DEVICE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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MDIO_SAM_CONFIG(n); \
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static struct mdio_sam_dev_data mdio_sam_dev_data##n; \
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DEVICE_DT_INST_DEFINE(n, \
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&mdio_sam_initialize, \
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NULL, \
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&mdio_sam_dev_data##n, \
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&mdio_sam_dev_config_##n, POST_KERNEL, \
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CONFIG_MDIO_INIT_PRIORITY, \
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&mdio_sam_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(MDIO_SAM_DEVICE)
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