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zephyr/soc/riscv/openisa_rv32m1
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David Leach bcd77a572c soc: riscv: rv32m1: kconfig: use RV32M1 TRNG as an entropy generator 
If the user requires an entropy generator to be activated, enable
the SoC TRNG as a source for the entropy.

Signed-off-by: David Leach <david.leach@nxp.com>
2019-11-08 15:38:57 +01:00
..
CMakeLists.txt riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
dts_fixup.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
Kconfig kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.defconfig soc: riscv: rv32m1: kconfig: use RV32M1 TRNG as an entropy generator 2019-11-08 15:38:57 +01:00
Kconfig.soc kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
linker.ld linker: move where we define _LINKER and _ASMLANGUAGE 2019-11-03 12:55:16 +01:00
soc.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00
soc.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_context.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_irq.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_offsets.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_ri5cy.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_zero_riscy.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
vector.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
wdog.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00