baf62b7a98
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP is implemented, causing issues related to included Zephyr linker files. Flash code still resides in flash for execution, but MMU/Cache handles it in such way that XIP might not (or should not) be used with current Zephyr approach. To address this problem, XIP configuration option is being removed from Espressif targets. Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
111 lines
3.1 KiB
Text
111 lines
3.1 KiB
Text
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_ESP32
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select XTENSA
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select CLOCK_CONTROL
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select DYNAMIC_INTERRUPTS
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select ARCH_HAS_GDBSTUB
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select ARCH_SUPPORTS_COREDUMP
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select PINCTRL
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select HAS_ESPRESSIF_HAL
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select CPU_HAS_FPU
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select HAS_PM
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select HAS_POWEROFF
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if SOC_SERIES_ESP32
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config ESP32_APPCPU_IRAM
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hex "ESP32 APPCPU IRAM size"
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depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU
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default 0x20000
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help
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Defines APPCPU IRAM area in bytes.
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config ESP32_APPCPU_DRAM
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hex "ESP32 APPCPU DRAM size"
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depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU
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default 0x10000
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help
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Defines APPCPU DRAM area in bytes.
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config SOC_ENABLE_APPCPU
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bool
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default y
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depends on IPM && SOC_ESP32_PROCPU
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depends on MBOX && SOC_ESP32_PROCPU
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help
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This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
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config ESP32_BT_RESERVE_DRAM
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hex "Bluetooth controller reserved RAM region"
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default 0xdb5c if BT
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default 0
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config ESP_HEAP_MEM_POOL_REGION_1_SIZE
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int "Internal DRAM region 1 mempool size"
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default 0 if MCUBOOT
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default 1024 if SOC_ESP32_PROCPU
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default 49152
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help
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ESP32 has two banks of size 192K and 128K which can be used
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as DRAM, system heap allocates area from region 0.
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This configuration can be used to add memory from region 1
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to heap and can be allocated using k_malloc.
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config ESP32_DEEP_SLEEP_WAKEUP_DELAY
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int "Extra delay in deep sleep wake stub (in us)"
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default 2000
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range 0 5000
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help
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When ESP32 exits deep sleep, the CPU and the flash chip are powered on
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at the same time. CPU will run deep sleep stub first, and then
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proceed to load code from flash. Some flash chips need sufficient
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time to pass between power on and first read operation. By default,
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without any extra delay, this time is approximately 900us, although
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some flash chip types need more than that.
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By default extra delay is set to 2000us. When optimizing startup time
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for applications which require it, this value may be reduced.
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If you are seeing "flash read err, 1000" message printed to the
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console after deep sleep reset, try increasing this value.
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config ESP32_EMAC
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bool
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default y if ETH_ESP32
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default y if MDIO_ESP32
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default n
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help
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Hidden option to enable the ESP32 Ethernet MAC driver.
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Both Ethernet and MDIO depend on this driver.
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This option allows enabling MDIO independently of Ethernet.
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if ESP32_EMAC
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config ETH_DMA_BUFFER_SIZE
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int "Ethernet DMA buffer size (Byte)"
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range 256 1600
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default 512
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help
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Set the size of each buffer used by Ethernet MAC DMA.
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config ETH_DMA_RX_BUFFER_NUM
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int "Amount of Ethernet DMA Rx buffers"
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range 3 30
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default 10
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help
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Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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config ETH_DMA_TX_BUFFER_NUM
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int "Amount of Ethernet DMA Tx buffers"
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range 3 30
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default 10
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help
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Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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endif # ESP32_EMAC config
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endif # SOC_SERIES_ESP32
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