ba982a0f85
register ostimer for cm33_cpu0/1 disable systick set ostimer per sec 1000000 times Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
440 lines
9.6 KiB
Text
440 lines
9.6 KiB
Text
/*
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* Copyright 2024-2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu1: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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sram: sram@10000000 {
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ranges = <0x0 0x10000000 0x780000
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0x20000000 0x30000000 0x780000>;
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};
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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};
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xspi2: spi@50411000 {
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reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>;
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};
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};
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pinctrl: pinctrl {
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compatible = "nxp,rt-iocon-pinctrl";
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};
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};
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&sram {
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#address-cells = <1>;
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#size-cells = <1>;
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/* RT7XX SRAM partitions are shared between code and data. Boards can
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* override the reg properties of either sram0 or sram_code nodes to
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* change the balance of SRAM allocation.
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*
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* The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data.
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* The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application.
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* The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application.
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*/
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sram_code: memory@600000{
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compatible = "mmio-sram";
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reg = <0x600000 DT_SIZE_K(512)>;
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};
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/* This partition is shared with code in RAM */
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sram_shared_code: memory@20058000{
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compatible = "mmio-sram";
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reg = <0x20058000 DT_SIZE_K(256)>;
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};
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sram0: memory@205C0000 {
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compatible = "mmio-sram";
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/* Only use 256K, align with SDK */
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reg = <0x205C0000 DT_SIZE_K(256)>;
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Note that the offsets here are relative to the base address.
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* The base addresses differ between non-secure (0x40000000)
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* and secure modes (0x50000000).
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*/
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lpadc0: adc@20c000 {
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compatible = "nxp,lpc-lpadc";
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reg = <0x20c000 0x304>;
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interrupts = <15 0>;
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status = "disabled";
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clk-divider = <1>;
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clk-source = <0>;
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voltage-ref= <1>;
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calibration-average = <128>;
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power-level = <0>;
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&clkctl3 MCUX_LPADC1_CLK>;
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};
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rstctl1: reset@40000 {
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compatible = "nxp,rstctl";
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reg = <0x40000 0x1000>;
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#reset-cells = <1>;
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};
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rstctl2: reset@67000 {
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compatible = "nxp,rstctl";
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reg = <0x67000 0x1000>;
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#reset-cells = <1>;
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};
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rstctl3: reset@60000 {
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compatible = "nxp,rstctl";
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reg = <0x60000 0x1000>;
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#reset-cells = <1>;
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};
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rstctl4: reset@a0000 {
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compatible = "nxp,rstctl";
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reg = <0xa0000 0x1000>;
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#reset-cells = <1>;
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};
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clkctl1: clkctl@41000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x41000 0x1000>;
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#clock-cells = <1>;
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};
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clkctl2: clkctl@65000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x65000 0x1000>;
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#clock-cells = <1>;
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};
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clkctl3: clkctl@61000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x61000 0x1000>;
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#clock-cells = <1>;
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};
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clkctl4: clkctl@a1000 {
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compatible = "nxp,lpc-syscon";
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reg = <0xa1000 0x1000>;
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#clock-cells = <1>;
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};
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ctimer5: ctimer@48000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x48000 0x1000>;
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interrupts = <7 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER5_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer6: ctimer@49000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x49000 0x1000>;
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interrupts = <8 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER6_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer7: ctimer@4a000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x4a000 0x1000>;
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interrupts = <9 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER7_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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syscon1: syscon@42000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x42000 0x1000>;
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#clock-cells = <1>;
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};
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syscon2: syscon@66000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x66000 0x1000>;
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#clock-cells = <1>;
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};
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syscon3: syscon@62000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x62000 0x1000>;
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#clock-cells = <1>;
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};
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syscon4: syscon@a2000 {
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compatible = "nxp,lpc-syscon";
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reg = <0xa2000 0x1000>;
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#clock-cells = <1>;
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};
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iocon1: iocon@64000 {
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compatible = "nxp,lpc-iocon";
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reg = <0x64000 0x1000>;
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status = "okay";
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};
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iocon2: iocon@a5000 {
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compatible = "nxp,lpc-iocon";
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reg = <0xa5000 0x1000>;
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status = "okay";
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};
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gpio8: gpio@320000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x320000 0x1000>;
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interrupts = <61 0>,<62 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&gpio8>;
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gpio-port-offest = <8>;
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};
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gpio9: gpio@322000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x322000 0x1000>;
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interrupts = <63 0>,<64 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&gpio9>;
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gpio-port-offest = <8>;
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};
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gpio10: gpio@324000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x324000 0x1000>;
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interrupts = <65 0>,<66 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&gpio10>;
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gpio-port-offest = <8>;
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};
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flexcomm17: flexcomm@326000 {
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compatible = "nxp,lp-flexcomm";
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reg = <0x326000 0x1000>;
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interrupts = <11 0>;
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status = "disabled";
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/* Empty ranges property implies parent and child address space is identical */
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ranges = <>;
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#address-cells = <1>;
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#size-cells = <1>;
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flexcomm17_lpuart17: uart@326000 {
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compatible = "nxp,lpuart";
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reg = <0x326000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
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status = "disabled";
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};
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flexcomm17_lpspi17: lpspi@326000 {
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compatible = "nxp,lpspi";
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reg = <0x326000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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tx-fifo-size = <8>;
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rx-fifo-size = <8>;
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status = "disabled";
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};
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flexcomm17_lpi2c17: lpi2c@326800 {
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compatible = "nxp,lpi2c";
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reg = <0x326800 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flexcomm18: flexcomm@327000 {
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compatible = "nxp,lp-flexcomm";
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reg = <0x327000 0x1000>;
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interrupts = <12 0>;
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status = "disabled";
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/* Empty ranges property implies parent and child address space is identical */
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ranges = <>;
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#address-cells = <1>;
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#size-cells = <1>;
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flexcomm18_lpuart18: uart@327000 {
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compatible = "nxp,lpuart";
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reg = <0x327000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
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status = "disabled";
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};
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flexcomm18_lpspi18: lpspi@327000 {
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compatible = "nxp,lpspi";
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reg = <0x327000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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tx-fifo-size = <8>;
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rx-fifo-size = <8>;
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status = "disabled";
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};
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flexcomm18_lpi2c18: lpi2c@327800 {
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compatible = "nxp,lpi2c";
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reg = <0x327800 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flexcomm19: flexcomm@328000 {
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compatible = "nxp,lp-flexcomm";
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reg = <0x328000 0x1000>;
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interrupts = <13 0>;
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status = "disabled";
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/* Empty ranges property implies parent and child address space is identical */
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ranges = <>;
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#address-cells = <1>;
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#size-cells = <1>;
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flexcomm19_lpuart19: uart@328000 {
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compatible = "nxp,lpuart";
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reg = <0x328000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
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status = "disabled";
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};
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flexcomm19_lpspi19: lpspi@328000 {
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compatible = "nxp,lpspi";
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reg = <0x328000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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tx-fifo-size = <8>;
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rx-fifo-size = <8>;
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status = "disabled";
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};
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flexcomm19_lpi2c19: lpi2c@328800 {
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compatible = "nxp,lpi2c";
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reg = <0x328800 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flexcomm20: flexcomm@329000 {
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compatible = "nxp,lp-flexcomm";
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reg = <0x329000 0x1000>;
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interrupts = <14 0>;
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status = "disabled";
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/* Empty ranges property implies parent and child address space is identical */
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ranges = <>;
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#address-cells = <1>;
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#size-cells = <1>;
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flexcomm20_lpuart20: uart@329000 {
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compatible = "nxp,lpuart";
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reg = <0x329000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
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status = "disabled";
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};
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flexcomm20_lpspi20: lpspi@329000 {
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compatible = "nxp,lpspi";
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reg = <0x329000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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tx-fifo-size = <8>;
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rx-fifo-size = <8>;
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status = "disabled";
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};
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flexcomm20_lpi2c20: lpi2c@329800 {
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compatible = "nxp,lpi2c";
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reg = <0x329800 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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/* LPFlexcomm15 only support LPI2C function. */
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lpi2c15: i2c@213000 {
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compatible = "nxp,lpi2c";
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reg = <0x213000 0x1000>;
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interrupts = <14 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkctl4 MCUX_LPI2C15_CLK>;
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status = "disabled";
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};
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os_timer_cpu1: timers@209000 {
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compatible = "nxp,os-timer";
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reg = <0x209000 0x1000>;
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interrupts = <30 0>;
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&systick {
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/*
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* RT700 cm33_cpu1 relies by default on the OS Timer for system
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* clock implementation, so the SysTick node is not to be enabled.
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*/
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status = "disabled";
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};
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