ae8b17d2bb
This is a driver for Intel Digital Microphone TODO: - volume rampup - TPLG config Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
486 lines
16 KiB
C
486 lines
16 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INTEL_DAI_DRIVER_DMIC_H__
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#define __INTEL_DAI_DRIVER_DMIC_H__
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#include <zephyr/sys/util_macro.h>
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/* bit operations macros */
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#define MASK(b_hi, b_lo) \
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(((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
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#define SET_BIT(b, x) (((x) & 1) << (b))
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#define SET_BITS(b_hi, b_lo, x) \
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(((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
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#define GET_BIT(b, x) \
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(((x) & (1ULL << (b))) >> (b))
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#define GET_BITS(b_hi, b_lo, x) \
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(((x) & MASK(b_hi, b_lo)) >> (b_lo))
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/* DMIC timestamping registers */
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#define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000
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#define TS_DMIC_LOCAL_OFFS_OFFSET 0x004
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#define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008
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#define TS_DMIC_LOCAL_WALCLK_OFFSET 0x010
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#define TS_DMIC_TSCC_OFFSET 0x018
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/* Timestamping */
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#define TIMESTAMP_BASE 0x00071800
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#define TS_DMIC_LOCAL_TSCTRL (TIMESTAMP_BASE + TS_DMIC_LOCAL_TSCTRL_OFFSET)
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#define TS_DMIC_LOCAL_OFFS (TIMESTAMP_BASE + TS_DMIC_LOCAL_OFFS_OFFSET)
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#define TS_DMIC_LOCAL_SAMPLE (TIMESTAMP_BASE + TS_DMIC_LOCAL_SAMPLE_OFFSET)
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#define TS_DMIC_LOCAL_WALCLK (TIMESTAMP_BASE + TS_DMIC_LOCAL_WALCLK_OFFSET)
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#define TS_DMIC_TSCC (TIMESTAMP_BASE + TS_DMIC_TSCC_OFFSET)
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#define TS_LOCAL_TSCTRL_NTK_BIT BIT(31)
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#define TS_LOCAL_TSCTRL_IONTE_BIT BIT(30)
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#define TS_LOCAL_TSCTRL_SIP_BIT BIT(8)
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#define TS_LOCAL_TSCTRL_HHTSE_BIT BIT(7)
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#define TS_LOCAL_TSCTRL_ODTS_BIT BIT(5)
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#define TS_LOCAL_TSCTRL_CDMAS(x) SET_BITS(4, 0, x)
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#define TS_LOCAL_OFFS_FRM GET_BITS(15, 12)
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#define TS_LOCAL_OFFS_CLK GET_BITS(11, 0)
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/* Digital Mic Shim Registers */
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#define DMICLCTL_OFFSET 0x04
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#define DMICIPPTR_OFFSET 0x08
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#define DMICSYNC_OFFSET 0x0C
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/* DMIC power ON bit */
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#define DMICLCTL_SPA BIT(0)
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/* DMIC Owner Select */
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#define DMICLCTL_OSEL(x) SET_BITS(25, 24, x)
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/* DMIC disable clock gating */
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#define DMIC_DCGD BIT(30)
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/* DMIC Command Sync */
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#define DMICSYNC_CMDSYNC BIT(16)
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/* DMIC Sync Go */
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#define DMICSYNC_SYNCGO BIT(24)
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/* DMIC Sync Period */
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#define DMICSYNC_SYNCPRD(x) SET_BITS(14, 0, x)
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/* Parameters used in modes computation */
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#define DMIC_HW_BITS_CIC 26
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#define DMIC_HW_BITS_FIR_COEF 20
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#define DMIC_HW_BITS_FIR_GAIN 20
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#define DMIC_HW_BITS_FIR_INPUT 22
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#define DMIC_HW_BITS_FIR_OUTPUT 24
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#define DMIC_HW_BITS_FIR_INTERNAL 26
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#define DMIC_HW_BITS_GAIN_OUTPUT 22
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#define DMIC_HW_FIR_LENGTH_MAX 250
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#define DMIC_HW_CIC_SHIFT_MIN -8
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#define DMIC_HW_CIC_SHIFT_MAX 4
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#define DMIC_HW_FIR_SHIFT_MIN 0
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#define DMIC_HW_FIR_SHIFT_MAX 8
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#define DMIC_HW_CIC_DECIM_MIN 5
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#define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
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#define DMIC_HW_FIR_DECIM_MIN 2
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#define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
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#define DMIC_HW_SENS_Q28 Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
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#define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
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#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
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#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
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/* DMIC register offsets */
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/* Global registers */
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#define OUTCONTROL0 0x0000
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#define OUTSTAT0 0x0004
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#define OUTDATA0 0x0008
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#define OUTCONTROL1 0x0100
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#define OUTSTAT1 0x0104
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#define OUTDATA1 0x0108
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#define PDM0 0x1000
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#define PDM0_COEFFICIENT_A 0x1400
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#define PDM0_COEFFICIENT_B 0x1800
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#define PDM1 0x2000
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#define PDM1_COEFFICIENT_A 0x2400
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#define PDM1_COEFFICIENT_B 0x2800
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#define PDM2 0x3000
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#define PDM2_COEFFICIENT_A 0x3400
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#define PDM2_COEFFICIENT_B 0x3800
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#define PDM3 0x4000
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#define PDM3_COEFFICIENT_A 0x4400
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#define PDM3_COEFFICIENT_B 0x4800
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#define PDM_COEF_RAM_A_LENGTH 0x0400
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#define PDM_COEF_RAM_B_LENGTH 0x0400
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/* Local registers in each PDMx */
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#define CIC_CONTROL 0x000
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#define CIC_CONFIG 0x004
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#define MIC_CONTROL 0x00c
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#define FIR_CONTROL_A 0x020
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#define FIR_CONFIG_A 0x024
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#define DC_OFFSET_LEFT_A 0x028
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#define DC_OFFSET_RIGHT_A 0x02c
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#define OUT_GAIN_LEFT_A 0x030
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#define OUT_GAIN_RIGHT_A 0x034
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#define FIR_CONTROL_B 0x040
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#define FIR_CONFIG_B 0x044
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#define DC_OFFSET_LEFT_B 0x048
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#define DC_OFFSET_RIGHT_B 0x04c
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#define OUT_GAIN_LEFT_B 0x050
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#define OUT_GAIN_RIGHT_B 0x054
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/* Register bits */
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/* OUTCONTROLx IPM bit fields style */
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#define OUTCONTROL0_BFTH_MAX 4 /* Max depth 16 */
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/* OUTCONTROL0 bits */
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#define OUTCONTROL0_TIE_BIT BIT(27)
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#define OUTCONTROL0_SIP_BIT BIT(26)
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#define OUTCONTROL0_FINIT_BIT BIT(25)
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#define OUTCONTROL0_FCI_BIT BIT(24)
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#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
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#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
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#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
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#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
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#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
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#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
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#define OUTCONTROL0_IPM(x) SET_BITS(17, 15, x)
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#define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
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#define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
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#define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
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#define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
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#define OUTCONTROL0_IPM_SOURCE_MODE(x) SET_BIT(6, x)
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#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
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#define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
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#define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
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#define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
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#define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
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#define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
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#define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
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#define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 15, x)
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#define OUTCONTROL0_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
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#define OUTCONTROL0_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
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#define OUTCONTROL0_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
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#define OUTCONTROL0_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
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#define OUTCONTROL0_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
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#define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
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/* OUTCONTROL1 bits */
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#define OUTCONTROL1_TIE_BIT BIT(27)
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#define OUTCONTROL1_SIP_BIT BIT(26)
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#define OUTCONTROL1_FINIT_BIT BIT(25)
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#define OUTCONTROL1_FCI_BIT BIT(24)
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#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
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#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
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#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
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#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
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#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
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#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
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#define OUTCONTROL1_IPM(x) SET_BITS(17, 15, x)
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#define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
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#define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
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#define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
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#define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
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#define OUTCONTROL1_IPM_SOURCE_MODE(x) SET_BIT(6, x)
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#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
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#define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
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#define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
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#define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
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#define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
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#define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
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#define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
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#define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 15, x)
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#define OUTCONTROL1_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
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#define OUTCONTROL1_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
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#define OUTCONTROL1_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
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#define OUTCONTROL1_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
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#define OUTCONTROL1_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
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#define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
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#define OUTCONTROLX_IPM_NUMSOURCES 4
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/* OUTSTAT0 bits */
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#define OUTSTAT0_AFE_BIT BIT(31)
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#define OUTSTAT0_ASNE_BIT BIT(29)
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#define OUTSTAT0_RFS_BIT BIT(28)
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#define OUTSTAT0_ROR_BIT BIT(27)
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#define OUTSTAT0_FL_MASK MASK(6, 0)
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/* OUTSTAT1 bits */
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#define OUTSTAT1_AFE_BIT BIT(31)
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#define OUTSTAT1_ASNE_BIT BIT(29)
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#define OUTSTAT1_RFS_BIT BIT(28)
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#define OUTSTAT1_ROR_BIT BIT(27)
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#define OUTSTAT1_FL_MASK MASK(6, 0)
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/* CIC_CONTROL bits */
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#define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
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#define CIC_CONTROL_CIC_START_B_BIT BIT(15)
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#define CIC_CONTROL_CIC_START_A_BIT BIT(14)
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#define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
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#define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
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#define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
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#define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
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#define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
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#define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
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#define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
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#define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
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#define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
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#define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
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#define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
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#define CIC_CONTROL_SOFT_RESET_GET(x) GET_BIT(16, x)
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#define CIC_CONTROL_CIC_START_B_GET(x) GET_BIT(15, x)
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#define CIC_CONTROL_CIC_START_A_GET(x) GET_BIT(14, x)
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#define CIC_CONTROL_MIC_B_POLARITY_GET(x) GET_BIT(3, x)
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#define CIC_CONTROL_MIC_A_POLARITY_GET(x) GET_BIT(2, x)
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#define CIC_CONTROL_MIC_MUTE_GET(x) GET_BIT(1, x)
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#define CIC_CONTROL_STEREO_MODE_GET(x) GET_BIT(0, x)
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/* CIC_CONFIG bits */
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#define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
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#define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
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/* CIC_CONFIG masks */
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#define CIC_CONFIG_CIC_SHIFT_MASK MASK(27, 24)
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#define CIC_CONFIG_COMB_COUNT_MASK MASK(15, 8)
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#define CIC_CONFIG_CIC_SHIFT_GET(x) GET_BITS(27, 24, x)
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#define CIC_CONFIG_COMB_COUNT_GET(x) GET_BITS(15, 8, x)
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/* MIC_CONTROL bits */
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#define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
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#define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
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#define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
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#define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
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#define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
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#define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
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#define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
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/* MIC_CONTROL masks */
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#define MIC_CONTROL_PDM_CLKDIV_MASK MASK(15, 8)
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#define MIC_CONTROL_PDM_CLKDIV_GET(x) GET_BITS(15, 8, x)
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#define MIC_CONTROL_PDM_SKEW_GET(x) GET_BITS(7, 4, x)
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#define MIC_CONTROL_PDM_CLK_EDGE_GET(x) GET_BIT(3, x)
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#define MIC_CONTROL_PDM_EN_B_GET(x) GET_BIT(1, x)
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#define MIC_CONTROL_PDM_EN_A_GET(x) GET_BIT(0, x)
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/* FIR_CONTROL_A bits */
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#define FIR_CONTROL_A_START_BIT BIT(7)
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#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
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#define FIR_CONTROL_A_MUTE_BIT BIT(1)
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#define FIR_CONTROL_A_START(x) SET_BIT(7, x)
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#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
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#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
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#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
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#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
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#define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x)
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#define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x)
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#define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x)
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#define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x)
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#define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x)
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/* FIR_CONFIG_A bits */
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#define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
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#define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
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#define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
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#define FIR_CONFIG_A_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
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#define FIR_CONFIG_A_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
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#define FIR_CONFIG_A_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
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/* DC offset compensation time constants */
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#define DCCOMP_TC0 0
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#define DCCOMP_TC1 1
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#define DCCOMP_TC2 2
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#define DCCOMP_TC3 3
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#define DCCOMP_TC4 4
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#define DCCOMP_TC5 5
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#define DCCOMP_TC6 6
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#define DCCOMP_TC7 7
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/* DC_OFFSET_LEFT_A bits */
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#define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
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/* DC_OFFSET_RIGHT_A bits */
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#define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
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/* OUT_GAIN_LEFT_A bits */
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#define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
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/* OUT_GAIN_RIGHT_A bits */
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#define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
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/* FIR_CONTROL_B bits */
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#define FIR_CONTROL_B_START_BIT BIT(7)
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#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
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#define FIR_CONTROL_B_MUTE_BIT BIT(1)
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#define FIR_CONTROL_B_START(x) SET_BIT(7, x)
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#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
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#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
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#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
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#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
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#define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x)
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#define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x)
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#define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x)
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#define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x)
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#define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x)
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/* FIR_CONFIG_B bits */
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#define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
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#define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
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#define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
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#define FIR_CONFIG_B_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
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#define FIR_CONFIG_B_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
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#define FIR_CONFIG_B_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
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/* DC_OFFSET_LEFT_B bits */
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#define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
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/* DC_OFFSET_RIGHT_B bits */
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#define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
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/* OUT_GAIN_LEFT_B bits */
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#define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
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/* OUT_GAIN_RIGHT_B bits */
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#define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
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/* FIR coefficients */
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#define FIR_COEF_A(x) SET_BITS(19, 0, x)
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#define FIR_COEF_B(x) SET_BITS(19, 0, x)
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/* Used for scaling FIR coefficients for HW */
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#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
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#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
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/* Internal precision in gains computation, e.g. Q4.28 in int32_t */
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#define DMIC_FIR_SCALE_Q 28
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/* Used in unmute ramp values calculation */
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#define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
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/* Hardwired log ramp parameters. The first value is the initial gain in
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* decibels. The default ramp time is provided by 1st order equation
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* ramp time = coef * samplerate + offset. The default ramp is 200 ms for
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* 48 kHz and 400 ms for 16 kHz.
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*/
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#define LOGRAMP_START_DB Q_CONVERT_FLOAT(-90, DB2LIN_FIXED_INPUT_QY)
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#define LOGRAMP_TIME_COEF_Q15 -205 /* dy/dx (16000,400) (48000,200) */
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#define LOGRAMP_TIME_OFFS_Q0 500 /* Offset for line slope */
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/* Limits for ramp time from topology */
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#define LOGRAMP_TIME_MIN_MS 10 /* Min. 10 ms */
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#define LOGRAMP_TIME_MAX_MS 1000 /* Max. 1s */
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/* Simplify log ramp step calculation equation with this constant term */
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#define LOGRAMP_CONST_TERM ((int32_t) \
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((int64_t)-LOGRAMP_START_DB * DMIC_UNMUTE_RAMP_US / 1000))
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/* Fractional shift for gain update. Gain format is Q2.30. */
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#define Q_SHIFT_GAIN_X_GAIN_COEF \
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(Q_SHIFT_BITS_32(30, DB2LIN_FIXED_OUTPUT_QY, 30))
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#define DMA_HANDSHAKE_DMIC_CH0 0
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#define DMA_HANDSHAKE_DMIC_CH1 1
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/* For NHLT DMIC configuration parsing */
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#define DMIC_HW_CONTROLLERS_MAX 4
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#define DMIC_HW_FIFOS_MAX 2
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struct nhlt_dmic_gateway_attributes {
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uint32_t dw;
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};
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struct nhlt_dmic_ts_group {
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uint32_t ts_group[4];
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};
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struct nhlt_dmic_clock_on_delay {
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uint32_t clock_on_delay;
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};
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struct nhlt_dmic_channel_ctrl_mask {
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uint32_t channel_ctrl_mask;
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};
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struct nhlt_pdm_ctrl_mask {
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uint32_t pdm_ctrl_mask;
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};
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struct nhlt_pdm_ctrl_cfg {
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uint32_t cic_control;
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uint32_t cic_config;
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uint32_t reserved0;
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uint32_t mic_control;
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uint32_t pdm_sdw_map;
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uint32_t reuse_fir_from_pdm;
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uint32_t reserved1[2];
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};
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struct nhlt_pdm_ctrl_fir_cfg {
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uint32_t fir_control;
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uint32_t fir_config;
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int32_t dc_offset_left;
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int32_t dc_offset_right;
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int32_t out_gain_left;
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int32_t out_gain_right;
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uint32_t reserved[2];
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};
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struct nhlt_pdm_fir_coeffs {
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int32_t fir_coeffs[0];
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};
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enum dai_dmic_frame_format {
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DAI_DMIC_FRAME_S16_LE = 0,
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DAI_DMIC_FRAME_S24_4LE,
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DAI_DMIC_FRAME_S32_LE,
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DAI_DMIC_FRAME_FLOAT,
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/* other formats here */
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DAI_DMIC_FRAME_S24_3LE,
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};
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/* Common data for all DMIC DAI instances */
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struct dai_dmic_global_shared {
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uint32_t active_fifos_mask; /* Bits (dai->index) are set to indicate active FIFO */
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uint32_t pause_mask; /* Bits (dai->index) are set to indicate driver pause */
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};
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struct dai_dmic_plat_fifo_data {
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uint32_t offset;
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|
uint32_t width;
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uint32_t depth;
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|
uint32_t watermark;
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uint32_t handshake;
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};
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struct dai_intel_dmic {
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struct dai_config dai_config_params;
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struct k_spinlock lock; /**< locking mechanism */
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|
int sref; /**< simple ref counter, guarded by lock */
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enum dai_state state; /* Driver component state */
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|
uint16_t enable[CONFIG_DAI_DMIC_HW_CONTROLLERS];/* Mic 0 and 1 enable bits array for PDMx */
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struct dai_dmic_plat_fifo_data fifo; /* dmic capture fifo stream */
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|
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/* hardware parameters */
|
|
uint32_t reg_base;
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|
uint32_t shim_base;
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|
int irq;
|
|
uint32_t flags;
|
|
};
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#endif /* __INTEL_DAI_DRIVER_DMIC_H__ */
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