aa6e21c24c
We want a _Swap() variant that can atomically release/restore a spinlock state in addition to the legacy irqlock. The function as it was is now named "_Swap_irqlock()", while _Swap() now refers to a spinlock and takes two arguments. The former will be going away once existing users (not that many! Swap() is an internal API, and the long port away from legacy irqlocking is going to be happening mostly in drivers) are ported to spinlocks. Obviously on uniprocessor setups, these produce identical code. But SMP requires that the correct API be used to maintain the global lock. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
428 lines
10 KiB
C
428 lines
10 KiB
C
/*
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* Copyright (c) 2017 Oticon A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* SW side of the IRQ handling
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*/
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#include <stdint.h>
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#include "irq_offload.h"
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#include "kernel_structs.h"
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#include "kernel_internal.h"
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#include "kswap.h"
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#include "irq_ctrl.h"
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#include "posix_core.h"
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#include "board_soc.h"
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#include "sw_isr_table.h"
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#include "soc.h"
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#include "bs_tracing.h"
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#include <tracing.h>
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#include "bstests.h"
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static bool CPU_will_be_awaken_from_WFE;
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typedef void (*normal_irq_f_ptr)(void *);
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typedef int (*direct_irq_f_ptr)(void);
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static struct _isr_list irq_vector_table[NRF_HW_NBR_IRQs];
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static int currently_running_irq = -1;
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const char *irqnames[] = { /*just for the traces*/
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"POWER_CLOCK", /*0 */
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"RADIO", /*1 */
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"UART0", /*2 */
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"SPI0_TWI0", /*3 */
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"SPI1_TWI1", /*4 */
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"NFCT", /*5 */
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"GPIOTE", /*6 */
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"ADC", /*7 */
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"TIMER0", /*8 */
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"TIMER1", /*9 */
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"TIMER2", /*10*/
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"RTC0", /*11*/
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"TEMP", /*12*/
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"RNG", /*13*/
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"ECB", /*14*/
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"CCM_AAR", /*15*/
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"WDT", /*16*/
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"RTC1", /*17*/
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"QDEC", /*18*/
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"LPCOMP", /*19*/
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"SWI0", /*20*/
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"SWI1", /*21*/
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"SWI2", /*22*/
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"SWI3", /*23*/
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"SWI4", /*24*/
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"SWI5", /*25*/
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"TIMER3", /*26*/
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"TIMER4", /*27*/
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"PWM0", /*28*/
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"PDM", /*29*/
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"MWU", /*30*/
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"PWM1", /*31*/
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"PWM2", /*32*/
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"SPIM2_SPIS2_SPI2", /*33*/
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"RTC2", /*34*/
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"I2S", /*35*/
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"FPU" /*36*/
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};
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static inline void vector_to_irq(int irq_nbr, int *may_swap)
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{
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/**
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* Call the test IRQ sniffer, and if it returns
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* true ignore the interrupt
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*/
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bool ret;
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ret = bst_irq_sniffer(irq_nbr);
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if (ret) {
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return;
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}
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bs_trace_raw_time(6, "Vectoring to irq %i (%s)\n", irq_nbr,
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irqnames[irq_nbr]);
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/*
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* As in this architecture an irq (code) executes in 0 time,
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* it is a bit senseless to call _int_latency_start/stop()
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*/
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/* _int_latency_start(); */
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sys_trace_isr_enter();
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if (irq_vector_table[irq_nbr].func == NULL) { /* LCOV_EXCL_BR_LINE */
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/* LCOV_EXCL_START */
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posix_print_error_and_exit("Received irq %i without a "
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"registered handler\n",
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irq_nbr);
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/* LCOV_EXCL_STOP */
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} else {
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if (irq_vector_table[irq_nbr].flags & ISR_FLAG_DIRECT) {
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*may_swap |= ((direct_irq_f_ptr)
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irq_vector_table[irq_nbr].func)();
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} else {
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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posix_irq_check_idle_exit();
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#endif
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((normal_irq_f_ptr)irq_vector_table[irq_nbr].func)
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(irq_vector_table[irq_nbr].param);
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*may_swap = 1;
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}
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}
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/* _int_latency_stop(); */
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bs_trace_raw_time(7, "Irq %i (%s) ended\n", irq_nbr, irqnames[irq_nbr]);
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}
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/**
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* When an interrupt is raised, this function is called to handle it and, if
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* needed, swap to a re-enabled thread
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*
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* Note that even that this function is executing in a Zephyr thread, it is
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* effectively the model of the interrupt controller passing context to the IRQ
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* handler and therefore its priority handling
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*/
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void posix_irq_handler(void)
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{
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u64_t irq_lock;
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int irq_nbr;
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static int may_swap;
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irq_lock = hw_irq_ctrl_get_current_lock();
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if (irq_lock) {
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/* "spurious" wakes can happen with interrupts locked */
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return;
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}
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if (_kernel.nested == 0) {
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may_swap = 0;
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}
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_kernel.nested++;
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while ((irq_nbr = hw_irq_ctrl_get_highest_prio_irq()) != -1) {
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int last_current_running_prio = hw_irq_ctrl_get_cur_prio();
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int last_running_irq = currently_running_irq;
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hw_irq_ctrl_set_cur_prio(hw_irq_ctrl_get_prio(irq_nbr));
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hw_irq_ctrl_clear_irq(irq_nbr);
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currently_running_irq = irq_nbr;
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vector_to_irq(irq_nbr, &may_swap);
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currently_running_irq = last_running_irq;
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hw_irq_ctrl_set_cur_prio(last_current_running_prio);
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}
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_kernel.nested--;
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/* Call swap if all the following is true:
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* 1) may_swap was enabled
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* 2) We are not nesting irq_handler calls (interrupts)
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* 3) Next thread to run in the ready queue is not this thread
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* 4) we are in a irq postfix (not just in a WFE)
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*/
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if (may_swap
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&& (hw_irq_ctrl_get_cur_prio() == 256)
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&& (CPU_will_be_awaken_from_WFE == false)
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&& (_kernel.ready_q.cache != _current)) {
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_Swap_irqlock(irq_lock);
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}
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}
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/**
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* Thru this function the IRQ controller can raise an immediate interrupt which
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* will interrupt the SW itself
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* (this function should only be called from the HW model code, from SW threads)
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*/
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void posix_irq_handler_im_from_sw(void)
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{
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/*
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* if a higher priority interrupt than the possibly currently running is
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* pending we go immediately into irq_handler() to vector into its
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* handler
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*/
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if (hw_irq_ctrl_get_highest_prio_irq() != -1) {
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if (!posix_is_cpu_running()) { /* LCOV_EXCL_BR_LINE */
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/* LCOV_EXCL_START */
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posix_print_error_and_exit("programming error: %s "
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"called from a HW model thread\n",
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__func__);
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/* LCOV_EXCL_STOP */
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}
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posix_irq_handler();
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}
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}
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/**
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* @brief Disable all interrupts on the CPU
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*
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* This routine disables interrupts. It can be called from either interrupt,
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* task or fiber level. This routine returns an architecture-dependent
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* lock-out key representing the "interrupt disable state" prior to the call;
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* this key can be passed to irq_unlock() to re-enable interrupts.
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*
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* The lock-out key should only be used as the argument to the irq_unlock()
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* API. It should never be used to manually re-enable interrupts or to inspect
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* or manipulate the contents of the source register.
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*
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* This function can be called recursively: it will return a key to return the
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* state of interrupt locking to the previous level.
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*
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* WARNINGS
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* Invoking a kernel routine with interrupts locked may result in
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* interrupts being re-enabled for an unspecified period of time. If the
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* called routine blocks, interrupts will be re-enabled while another
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* thread executes, or while the system is idle.
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*
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* The "interrupt disable state" is an attribute of a thread. Thus, if a
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* fiber or task disables interrupts and subsequently invokes a kernel
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* routine that causes the calling thread to block, the interrupt
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* disable state will be restored when the thread is later rescheduled
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* for execution.
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*
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* @return An architecture-dependent lock-out key representing the
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* "interrupt disable state" prior to the call.
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*
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*/
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unsigned int posix_irq_lock(void)
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{
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return hw_irq_ctrl_change_lock(true);
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}
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unsigned int _arch_irq_lock(void)
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{
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return posix_irq_lock();
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}
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/**
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*
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* @brief Enable all interrupts on the CPU
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*
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* This routine re-enables interrupts on the CPU. The @a key parameter is a
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* board-dependent lock-out key that is returned by a previous invocation of
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* board_irq_lock().
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*
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* This routine can be called from either interrupt, task or fiber level.
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*
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* @return N/A
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*
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*/
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void posix_irq_unlock(unsigned int key)
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{
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hw_irq_ctrl_change_lock(key);
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}
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void _arch_irq_unlock(unsigned int key)
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{
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posix_irq_unlock(key);
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}
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void posix_irq_full_unlock(void)
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{
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hw_irq_ctrl_change_lock(false);
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}
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void _arch_irq_enable(unsigned int irq)
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{
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hw_irq_ctrl_enable_irq(irq);
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}
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void _arch_irq_disable(unsigned int irq)
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{
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hw_irq_ctrl_disable_irq(irq);
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}
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int _arch_irq_is_enabled(unsigned int irq)
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{
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return hw_irq_ctrl_is_irq_enabled(irq);
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}
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void _arch_isr_direct_header(void)
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{
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/* Nothing to be done */
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}
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int posix_get_current_irq(void)
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{
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return currently_running_irq;
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}
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/**
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* Configure a static interrupt.
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*
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* _isr_declare will populate the interrupt table table with the interrupt's
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* parameters, the vector table and the software ISR table.
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*
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* We additionally set the priority in the interrupt controller at
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* runtime.
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*
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* @param irq_p IRQ line number
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* @param flags [plug it directly (1), or as a SW managed interrupt (0)]
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ options
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*/
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void _isr_declare(unsigned int irq_p, int flags, void isr_p(void *),
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void *isr_param_p)
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{
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irq_vector_table[irq_p].irq = irq_p;
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irq_vector_table[irq_p].func = isr_p;
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irq_vector_table[irq_p].param = isr_param_p;
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irq_vector_table[irq_p].flags = flags;
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}
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/*
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* Lower values take priority over higher values.
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*
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* @return N/A
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*/
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void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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hw_irq_ctrl_prio_set(irq, prio);
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}
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/**
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* Similar to ARM's NVIC_SetPendingIRQ
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* set a pending IRQ from SW
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*
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* Note that this will interrupt immediately if the interrupt is not masked and
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* IRQs are not locked, and this interrupt has higher priority than a possibly
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* currently running interrupt
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*/
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void posix_sw_set_pending_IRQ(unsigned int IRQn)
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{
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hw_irq_ctrl_raise_im_from_sw(IRQn);
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}
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/**
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* Similar to ARM's NVIC_ClearPendingIRQ
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* clear a pending irq from SW
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*/
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void posix_sw_clear_pending_IRQ(unsigned int IRQn)
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{
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hw_irq_ctrl_clear_irq(IRQn);
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}
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/**
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* Storage for functions offloaded to IRQ
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*/
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static irq_offload_routine_t off_routine;
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static void *off_parameter;
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/**
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* IRQ handler for the SW interrupt assigned to irq_offload()
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*/
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static void offload_sw_irq_handler(void *a)
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{
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ARG_UNUSED(a);
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off_routine(off_parameter);
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}
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/**
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* @brief Run a function in interrupt context
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*
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* Raise the SW IRQ assigned to handled this
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*/
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void irq_offload(irq_offload_routine_t routine, void *parameter)
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{
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off_routine = routine;
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off_parameter = parameter;
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_isr_declare(OFFLOAD_SW_IRQ, 0, offload_sw_irq_handler, NULL);
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_arch_irq_enable(OFFLOAD_SW_IRQ);
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posix_sw_set_pending_IRQ(OFFLOAD_SW_IRQ);
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_arch_irq_disable(OFFLOAD_SW_IRQ);
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}
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/**
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* Replacement for ARMs NVIC_SetPendingIRQ()
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*
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* Sets the interrupt IRQn as pending
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* Note:
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* This will interrupt immediately if the interrupt
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* is not masked and irqs are not locked, and this interrupt is higher
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* priority than a possibly currently running interrupt
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*/
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void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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hw_irq_ctrl_raise_im_from_sw(IRQn);
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}
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/**
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* Replacement for ARMs NVIC_ClearPendingIRQ()
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* Clear pending interrupt IRQn
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*/
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void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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hw_irq_ctrl_clear_irq(IRQn);
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}
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/*
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* Very simple model of the WFE and SEV ARM instructions
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* which seems good enough for the Nordic controller
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*/
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static bool CPU_event_set_flag;
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void __WFE(void)
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{
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if (CPU_event_set_flag == false) {
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CPU_will_be_awaken_from_WFE = true;
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posix_halt_cpu();
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CPU_will_be_awaken_from_WFE = false;
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}
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CPU_event_set_flag = false;
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}
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void __SEV(void)
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{
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CPU_event_set_flag = true;
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}
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