a71d6f2c0c
This is the initial Zephyr support for Intel SoC FPGA Agilex support. Agilex has quad-core 64-bit Arm Cortex*-A53. This patch build Zephyr for Agilex development kit with 256KB SDRAM and support hello_world sample code. The Zephyr will need to be loaded by Intel Arm Trusted Firmware (ATF). Agilex Zephyr boot flow: FSBL:ATF BL2(EL3) -> SSBL:ATF BL31(EL3) -> OS:Zephyr(EL2->EL1) Intel ATF can be loaded from: https://github.com/altera-opensource/arm-trusted-firmware.git Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
79 lines
2.7 KiB
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79 lines
2.7 KiB
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.. _intel_socfpga_agilex_socdk:
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Intel Agilex SoC Development Kit
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#################################
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Overview
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********
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The Intel Agilex SoC Development Kit offers a complete design environment
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that includes both hardware and software for developing Intel Agilex
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F-Series FPGA designs. This kit is recommended for developing custom
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Arm* processor-based SoC designs and evaluating transceiver performance.
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Hardware
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********
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The Intel Agilex SoC Development Kit supports the following physical features:
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- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the
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quad-core Arm Cortex-A53 processor
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- On-board 8 GB DDR4 memory
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- On-board JTAG Intel FPGA Download Cable II
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- QSPI flash daughtercard
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- HPS OOBE daughtercard with UART and SD Card support
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Supported Features
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==================
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The Intel Agilex SoC Development Kit configuration supports the following
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hardware features:
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+-----------+------------+--------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+======================================+
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| GIC-400 | on-chip | GICv2 interrupt controller |
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+-----------+------------+--------------------------------------+
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| ARM TIMER | on-chip | System Clock |
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+-----------+------------+--------------------------------------+
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| UART | on-chip | NS16550 compatible serial port |
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+-----------+------------+--------------------------------------+
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Other hardware features are not supported by the Zephyr kernel.
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The default configuration can be found in the defconfig file:
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``boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig``
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Programming and Debugging
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*************************
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Boot Flow
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=========
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Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF).
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ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage
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boot loader (SSBL).
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Zephyr boot flow:
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ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1)
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Intel Arm Trusted Firmware (ATF) can be downloaded from github:
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`altera-opensource/arm-trusted-firmware <https://github.com/altera-opensource/arm-trusted-firmware.git>`_
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Flashing
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========
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Zephyr image can be loaded in DDR memory at address 0x10000000 from
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SD Card or QSPI Flash in ATF BL2.
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Debugging
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=========
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The Intel Agilex SoC Development Kit includes one JTAG connector on
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board, connect it to Intel USB blaster download cables for debugging.
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Zephyr applications running on the Cortex-A53 core can be tested by
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observing UART console output.
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References
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==========
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`Intel Agilex Transceiver-SoC Development Kit <https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-agf-si.html>`_
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