a4633da9f5
Add mcux 2.4.0 drivers and device header files for mimxrt1061 and mimxrt1060. Updates several drivers that were already imported for other SoCs but also apply to mimxrt1061 and mimxrt1062. Origins: NXP MCUxpresso SDK 2.4.0 URL: mcuxpresso.nxp.com Maintained-by: External Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
551 lines
24 KiB
C
551 lines
24 KiB
C
/*
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_COMMON_H_
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#define _FSL_COMMON_H_
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#if defined(__ICCARM__)
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#include <stddef.h>
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#endif
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#include "fsl_device_registers.h"
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/*!
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* @addtogroup ksdk_common
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Construct a status code value from a group and code number. */
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#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
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/*! @brief Construct the version number for drivers. */
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#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
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/*! @name Driver version */
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/*@{*/
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/*! @brief common driver version 2.0.0. */
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#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* Debug console type definition. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
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#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
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/*! @brief Status group numbers. */
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enum _status_groups
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{
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kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
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kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
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kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
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kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
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kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
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kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
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kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
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kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
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kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
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kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
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kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
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kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
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kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
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kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
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kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
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kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
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kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
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kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
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kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
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kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
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kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
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kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
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kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
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kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
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kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
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kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
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kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
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kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
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kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
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kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
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kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
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kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
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kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
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kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
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kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
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kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
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kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
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kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
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kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
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kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
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kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
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kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
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kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
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kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
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kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
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kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
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kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
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kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
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kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
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kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
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kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
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kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
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kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
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kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
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kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
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kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
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kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
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kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
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kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
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kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
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kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
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kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
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kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
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kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
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kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
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kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
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kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
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kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
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kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
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};
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/*! @brief Generic status return codes. */
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enum _generic_status
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{
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kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
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kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
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kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
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kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
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kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
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kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
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kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
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};
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/*! @brief Type used for all status and error return values. */
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typedef int32_t status_t;
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/*
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* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
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* defined in previous of this file.
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*/
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#include "fsl_clock.h"
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/*
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* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
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*/
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#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
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(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
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#include "fsl_reset.h"
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#endif
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/*
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* Macro guard for whether to use default weak IRQ implementation in drivers
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*/
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#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
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#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
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#endif
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/*! @name Min/max macros */
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/* @{ */
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#if !defined(MIN)
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#endif
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#if !defined(MAX)
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#endif
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/* @} */
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/*! @brief Computes the number of elements in an array. */
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#if !defined(ARRAY_SIZE)
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#endif
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/*! @name UINT16_MAX/UINT32_MAX value */
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/* @{ */
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#if !defined(UINT16_MAX)
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#define UINT16_MAX ((uint16_t)-1)
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#endif
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#if !defined(UINT32_MAX)
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#define UINT32_MAX ((uint32_t)-1)
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#endif
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/* @} */
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/*! @name Timer utilities */
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/* @{ */
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/*! Macro to convert a microsecond period to raw count value */
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#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
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/*! Macro to convert a raw count value to microsecond */
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#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
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/*! Macro to convert a millisecond period to raw count value */
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#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
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/*! Macro to convert a raw count value to millisecond */
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#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
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/* @} */
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/*! @name Alignment variable definition macros */
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/* @{ */
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#if (defined(__ICCARM__))
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/**
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* Workaround to disable MISRA C message suppress warnings for IAR compiler.
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* http://supp.iar.com/Support/?note=24725
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*/
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_Pragma("diag_suppress=Pm120")
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#define SDK_PRAGMA(x) _Pragma(#x)
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_Pragma("diag_error=Pm120")
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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/*! Macro to define a variable with L1 d-cache line size alignment */
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#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
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#endif
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/*! Macro to define a variable with L2 cache line size alignment */
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#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
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#endif
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#elif defined(__ARMCC_VERSION)
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
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/*! Macro to define a variable with L1 d-cache line size alignment */
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#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
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#endif
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/*! Macro to define a variable with L2 cache line size alignment */
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#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
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#endif
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#elif defined(__GNUC__)
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/*! Macro to define a variable with alignbytes alignment */
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#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
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/*! Macro to define a variable with L1 d-cache line size alignment */
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#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
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#endif
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/*! Macro to define a variable with L2 cache line size alignment */
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#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
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#endif
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#else
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#error Toolchain not supported
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#define SDK_ALIGN(var, alignbytes) var
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#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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#define SDK_L1DCACHE_ALIGN(var) var
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#endif
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#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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#define SDK_L2CACHE_ALIGN(var) var
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#endif
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#endif
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/*! Macro to change a value to a given size aligned value */
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#define SDK_SIZEALIGN(var, alignbytes) \
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((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
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/* @} */
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/*! @name Non-cacheable region definition macros */
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/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
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* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
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* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
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* will be initialized to zero in system startup.
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*/
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/* @{ */
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#if (defined(__ICCARM__))
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#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
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#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
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#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
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#else
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#define AT_NONCACHEABLE_SECTION(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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#define AT_NONCACHEABLE_SECTION_INIT(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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#endif
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#elif(defined(__ARMCC_VERSION))
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#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
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#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
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#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
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#else
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#define AT_NONCACHEABLE_SECTION(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
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#define AT_NONCACHEABLE_SECTION_INIT(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
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#endif
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#elif(defined(__GNUC__))
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/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
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* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
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*/
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#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
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#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
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#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
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#else
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#define AT_NONCACHEABLE_SECTION(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
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#define AT_NONCACHEABLE_SECTION_INIT(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
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#endif
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#else
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#error Toolchain not supported.
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#define AT_NONCACHEABLE_SECTION(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
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#define AT_NONCACHEABLE_SECTION_INIT(var) var
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#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
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#endif
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/* @} */
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/*! @name Time sensitive region */
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/* @{ */
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#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
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#if (defined(__ICCARM__))
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#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
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#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
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#elif(defined(__ARMCC_VERSION))
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#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
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#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
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#elif(defined(__GNUC__))
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#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
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#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
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#else
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#error Toolchain not supported.
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#endif /* defined(__ICCARM__) */
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#else
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#if (defined(__ICCARM__))
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#define AT_QUICKACCESS_SECTION_CODE(func) func
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#define AT_QUICKACCESS_SECTION_DATA(func) func
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#elif(defined(__ARMCC_VERSION))
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#define AT_QUICKACCESS_SECTION_CODE(func) func
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#define AT_QUICKACCESS_SECTION_DATA(func) func
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#elif(defined(__GNUC__))
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#define AT_QUICKACCESS_SECTION_CODE(func) func
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#define AT_QUICKACCESS_SECTION_DATA(func) func
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#else
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#error Toolchain not supported.
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#endif
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#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
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/* @} */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C"
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{
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#endif
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/*!
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* @brief Enable specific interrupt.
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*
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* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
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|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
* to NVIC first then routed to core.
|
|
*
|
|
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
* @retval kStatus_Success Interrupt enabled successfully
|
|
* @retval kStatus_Fail Failed to enable the interrupt
|
|
*/
|
|
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
|
{
|
|
if (NotAvail_IRQn == interrupt)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
#endif
|
|
|
|
#if defined(__GIC_PRIO_BITS)
|
|
GIC_EnableIRQ(interrupt);
|
|
#else
|
|
NVIC_EnableIRQ(interrupt);
|
|
#endif
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* @brief Disable specific interrupt.
|
|
*
|
|
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
|
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
|
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
|
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
|
* to NVIC first then routed to core.
|
|
*
|
|
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
|
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
* @retval kStatus_Success Interrupt disabled successfully
|
|
* @retval kStatus_Fail Failed to disable the interrupt
|
|
*/
|
|
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
|
{
|
|
if (NotAvail_IRQn == interrupt)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
|
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
#endif
|
|
|
|
#if defined(__GIC_PRIO_BITS)
|
|
GIC_DisableIRQ(interrupt);
|
|
#else
|
|
NVIC_DisableIRQ(interrupt);
|
|
#endif
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* @brief Disable the global IRQ
|
|
*
|
|
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
|
* register for the EnableGlobalIRQ().
|
|
*
|
|
* @return Current primask value.
|
|
*/
|
|
static inline uint32_t DisableGlobalIRQ(void)
|
|
{
|
|
#if defined(CPSR_I_Msk)
|
|
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
|
|
|
__disable_irq();
|
|
|
|
return cpsr;
|
|
#else
|
|
uint32_t regPrimask = __get_PRIMASK();
|
|
|
|
__disable_irq();
|
|
|
|
return regPrimask;
|
|
#endif
|
|
}
|
|
|
|
/*!
|
|
* @brief Enaable the global IRQ
|
|
*
|
|
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
|
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
|
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
|
*
|
|
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
|
* DisableGlobalIRQ().
|
|
*/
|
|
static inline void EnableGlobalIRQ(uint32_t primask)
|
|
{
|
|
#if defined(CPSR_I_Msk)
|
|
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
|
#else
|
|
__set_PRIMASK(primask);
|
|
#endif
|
|
}
|
|
|
|
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
|
/*!
|
|
* @brief install IRQ handler
|
|
*
|
|
* @param irq IRQ number
|
|
* @param irqHandler IRQ handler address
|
|
* @return The old IRQ handler address
|
|
*/
|
|
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
|
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
|
|
|
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
|
/*!
|
|
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
|
*
|
|
* Enable the interrupt for wake-up from deep sleep mode.
|
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
* making these wake-ups possible.
|
|
*
|
|
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
*/
|
|
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
|
|
|
/*!
|
|
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
|
*
|
|
* Disable the interrupt for wake-up from deep sleep mode.
|
|
* Some interrupts are typically used in sleep mode only and will not occur during
|
|
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
|
* those clocks (significantly increasing power consumption in the reduced power mode),
|
|
* making these wake-ups possible.
|
|
*
|
|
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
|
*
|
|
* @param interrupt The IRQ number.
|
|
*/
|
|
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
|
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
|
|
|
/*!
|
|
* @brief Allocate memory with given alignment and aligned size.
|
|
*
|
|
* This is provided to support the dynamically allocated memory
|
|
* used in cache-able region.
|
|
* @param size The length required to malloc.
|
|
* @param alignbytes The alignment size.
|
|
* @retval The allocated memory.
|
|
*/
|
|
void *SDK_Malloc(size_t size, size_t alignbytes);
|
|
|
|
/*!
|
|
* @brief Free memory.
|
|
*
|
|
* @param ptr The memory to be release.
|
|
*/
|
|
void SDK_Free(void *ptr);
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
/*! @} */
|
|
|
|
#endif /* _FSL_COMMON_H_ */
|