a097cdc4fe
Currently this code related to how to configure the flash size and address when using flexspi to XIP is copy pasted in all sort of places and ways all over the tree, let's clean this up and have single point of control over this configuration. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
47 lines
974 B
Text
47 lines
974 B
Text
# MIMXRT1170-EVK board
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# Copyright 2021,2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MIMXRT1170_EVK
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# Use External Memory Configuration Data (XMCD) by default when booting primary core (M7)
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config EXTERNAL_MEM_CONFIG_DATA
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default y if CPU_CORTEX_M7
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config NXP_IMX_EXTERNAL_SDRAM
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default y if CPU_CORTEX_M7
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if SECOND_CORE_MCUX && CPU_CORTEX_M4
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config BUILD_OUTPUT_INFO_HEADER
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default y
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DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
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# Adjust the offset of the output image if building for RT11xx SOC
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config BUILD_OUTPUT_ADJUST_LMA
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default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
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$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
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$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
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endif
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if DISK_DRIVERS
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config IMX_USDHC_DAT3_PWR_TOGGLE
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default y
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endif # DISK_DRIVERS
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if NETWORKING
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config NET_L2_ETHERNET
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default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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endif
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