9f02634d3f
Configure the main internal Regulator output voltage for best performance on STM32N6. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32N6 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <zephyr/logging/log.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_icache.h>
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#include <cmsis_core.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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extern char _vector_start[];
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void *g_pfnVectors = (void *)_vector_start;
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#if defined(CONFIG_SOC_RESET_HOOK)
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void soc_reset_hook(void)
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{
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/* This is provided by STM32Cube HAL */
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SystemInit();
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}
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#endif
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*
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* @return 0
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*/
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void soc_early_init_hook(void)
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{
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/* Enable caches */
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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SystemCoreClock = 64000000;
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/* Enable PWR */
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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/* Set the main internal Regulator output voltage for best performance */
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
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/* Enable IOs */
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LL_PWR_EnableVddIO2();
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LL_PWR_EnableVddIO3();
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LL_PWR_EnableVddIO4();
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LL_PWR_EnableVddIO5();
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/* Set Vdd IO2 and IO3 to 1.8V */
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LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
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LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
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}
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