9e44f59e9a
This adds a new driver for Renesas RZ/T2M. The driver allows configuration of pin direction, pull up/down resistors, drive strength and slew rate, and selection of function for a pin. Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
122 lines
2.8 KiB
Text
122 lines
2.8 KiB
Text
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "renesas,rzt2m-dev";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <1>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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soc {
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compatible = "renesas,rzt2m-soc";
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interrupt-parent = <&gic>;
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gic: interrupt-controller@94000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x94000000 0x10000>,
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<0x94100000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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cpu0_atcm: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(512)>;
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};
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cpu0_btcm: memory@100000 {
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compatible = "mmio-sram";
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reg = <0x00100000 DT_SIZE_K(64)>;
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};
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sram0: memory@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 DT_SIZE_M(2)>;
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};
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gsc: gsc@c0060000 {
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/* Global System Counter */
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compatible = "syscon";
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reg = <0xc0060000 0x30>;
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reg-io-width = <4>;
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};
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prcrn: prcrn@80281a10 {
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/* Non-safety area */
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compatible = "syscon";
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reg = <0x80281a10 0x10>;
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reg-io-width = <4>;
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};
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prcrs: prcrs@81281a00 {
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/* Safety area */
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compatible = "syscon";
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reg = <0x81281a00 0x10>;
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reg-io-width = <4>;
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};
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uart0: serial@80001000 {
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compatible = "renesas,rzt2m-uart";
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reg = <0x80001000 0x1000>;
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current-speed = <115200>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "rx_err", "rx", "tx", "tx_end";
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status = "disabled";
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};
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uart3: serial@80001c00 {
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compatible = "renesas,rzt2m-uart";
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reg = <0x80001c00 0x1000>;
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current-speed = <115200>;
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "rx_err", "rx", "tx", "tx_end";
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status = "disabled";
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};
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pinctrl: pinctrl@800a0000 {
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compatible = "renesas,rzt2m-pinctrl";
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reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
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reg-names = "port_nsr", "ptadr";
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};
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};
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};
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