9dc7640ede
The generic SPI GPIO chip select support now respects devicetree flags for signal active level. Update all cs-gpios properties to specify active low. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
217 lines
4 KiB
Text
217 lines
4 KiB
Text
/*
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* Copyright (c) 2020, Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <arm/armv8-m.dtsi>
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/ {
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aliases {
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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};
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chosen {
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zephyr,flash-controller = &iap;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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cpu@1 {
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compatible = "arm,cortex-m33";
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reg = <1>;
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};
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};
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};
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&sram {
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#address-cells = <1>;
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#size-cells = <1>;
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sramx: memory@4000000 {
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(32)>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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sram1: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram2: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(64)>;
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};
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sram3: memory@20030000 {
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compatible = "mmio-sram";
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reg = <0x20030000 DT_SIZE_K(64)>;
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};
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sram4: memory@20040000 {
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/* Conencted to USB bus*/
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compatible = "mmio-sram";
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reg = <0x20040000 DT_SIZE_K(16)>;
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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iap: flash-controller@34000 {
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compatible = "nxp,lpc-iap";
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label = "FLASH_IAP";
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reg = <0x34000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "MCUX_FLASH";
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reg = <0x0 DT_SIZE_K(630)>;
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erase-block-size = <512>;
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write-block-size = <512>;
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};
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flash_reserved: flash@9D800 {
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compatible = "soc-nv-flash";
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reg = <0x9D800 DT_SIZE_K(10)>;
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status = "disabled";
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};
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boot_rom: flash@3000000 {
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compatible = "soc-nv-flash";
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reg = <0x3000000 DT_SIZE_K(128)>;
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};
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};
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gpio0: gpio@0 {
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compatible = "nxp,lpc-gpio";
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reg = <0x8c000 0x2488>;
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interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,lpc-gpio";
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reg = <0x8c000 0x2488>;
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interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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flexcomm0: flexcomm@86000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x86000 0x1000>;
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interrupts = <14 0>;
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label = "FLEXCOMM_0";
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status = "disabled";
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};
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flexcomm1: flexcomm@87000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x87000 0x1000>;
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interrupts = <15 0>;
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label = "FLEXCOMM_1";
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status = "disabled";
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};
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flexcomm2: flexcomm@88000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x88000 0x1000>;
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interrupts = <16 0>;
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label = "FLEXCOMM_2";
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status = "disabled";
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};
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flexcomm3: flexcomm@89000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x89000 0x1000>;
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interrupts = <17 0>;
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label = "FLEXCOMM_3";
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status = "disabled";
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};
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flexcomm4: flexcomm@8a000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x8a000 0x1000>;
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interrupts = <18 0>;
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label = "FLEXCOMM_4";
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status = "disabled";
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};
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flexcomm5: flexcomm@96000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x96000 0x1000>;
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interrupts = <19 0>;
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label = "FLEXCOMM_5";
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status = "disabled";
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};
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flexcomm6: flexcomm@97000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x97000 0x1000>;
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interrupts = <20 0>;
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label = "FLEXCOMM_6";
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status = "disabled";
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};
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flexcomm7: flexcomm@98000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x98000 0x1000>;
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interrupts = <21 0>;
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label = "FLEXCOMM_7";
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status = "disabled";
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};
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hs_lspi: spi@9f000 {
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compatible = "nxp,lpc-spi";
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
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<&gpio1 1 GPIO_ACTIVE_LOW>,
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<&gpio1 12 GPIO_ACTIVE_LOW>,
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<&gpio1 26 GPIO_ACTIVE_LOW>;
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reg = <0x9f000 0x1000>;
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interrupts = <59 0>;
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label = "HS_LSPI";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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rng: rng@3a000 {
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compatible = "nxp,lpc-rng";
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reg = <0x3a000 0x1000>;
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status = "okay";
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label = "RNG";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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