9c62a4a01f
The base address and IRQ line are static per SoC, so there is no need to make them configurable in Kconfig. Change-Id: Ib78401ff136c29642356f5bda9d6cd3e5c98bece Signed-off-by: Daniel Leung <daniel.leung@intel.com>
432 lines
10 KiB
C
432 lines
10 KiB
C
/*
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* Copyright (c) 2016, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for the Freescale K64 GPIO module.
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*/
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#include <errno.h>
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <gpio.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <pinmux/frdm_k64f/pinmux_k64.h>
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#include "gpio_k64.h"
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static int gpio_k64_config(struct device *dev,
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int access_op, uint32_t pin, int flags)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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uint32_t value;
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uint32_t setting;
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uint8_t i;
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/* check for an invalid pin configuration */
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -ENOTSUP;
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}
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/*
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* Setup direction register:
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* 0 - pin is input, 1 - pin is output
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*/
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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sys_clear_bit((cfg->gpio_base_addr +
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GPIO_K64_DIR_OFFSET), pin);
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} else { /* GPIO_DIR_OUT */
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sys_set_bit((cfg->gpio_base_addr +
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GPIO_K64_DIR_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0x0;
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} else { /* GPIO_DIR_OUT */
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value = 0xFFFFFFFF;
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}
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sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
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}
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/*
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* Set up pullup/pulldown configuration, in Port Control module:
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*/
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_DN);
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_NORMAL) {
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setting = K64_PINMUX_PULL_DISABLE;
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} else {
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return -ENOTSUP;
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}
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/*
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* Set up interrupt configuration, in Port Control module:
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*/
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if (flags & GPIO_INT) {
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/* edge or level */
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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setting |= K64_PINMUX_INT_RISING;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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setting |= K64_PINMUX_INT_BOTH_EDGE;
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} else {
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setting |= K64_PINMUX_INT_FALLING;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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setting |= K64_PINMUX_INT_HIGH;
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} else {
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setting |= K64_PINMUX_INT_LOW;
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}
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}
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}
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/* write pull-up/-down and, if set, interrupt configuration settings */
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if (access_op == GPIO_ACCESS_BY_PIN) {
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value = sys_read32((cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(pin)));
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/* clear, then set configuration values */
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value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
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if (flags & GPIO_INT) {
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value &= ~K64_PINMUX_INT_MASK;
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}
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value |= setting;
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sys_write32(value, (cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(pin)));
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} else { /* GPIO_ACCESS_BY_PORT */
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for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
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/* clear, then set configuration values */
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value = sys_read32((cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(i)));
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value &= ~(K64_PINMUX_PULL_EN_MASK |
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K64_PINMUX_PULL_SEL_MASK);
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if (flags & GPIO_INT) {
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value &= ~K64_PINMUX_INT_MASK;
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}
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value |= setting;
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sys_write32(value, (cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(i)));
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}
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}
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return 0;
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}
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static int gpio_k64_write(struct device *dev,
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int access_op, uint32_t pin, uint32_t value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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sys_set_bit((cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET), pin);
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} else {
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sys_clear_bit((cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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sys_write32(value, (cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET));
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}
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return 0;
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}
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static int gpio_k64_read(struct device *dev,
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int access_op, uint32_t pin, uint32_t *value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (*value & BIT(pin)) >> pin;
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}
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/* nothing more to do for GPIO_ACCESS_BY_PORT */
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return 0;
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}
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static int gpio_k64_set_callback(struct device *dev, gpio_callback_t callback)
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{
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struct gpio_k64_data *data = dev->driver_data;
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data->callback_func = callback;
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return 0;
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}
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static int gpio_k64_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_k64_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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} else {
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data->port_callback_enable = 1;
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}
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return 0;
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}
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static int gpio_k64_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_k64_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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data->port_callback_enable = 0;
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}
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return 0;
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}
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/**
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* @brief Handler for port interrupts
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* @param dev Pointer to device structure for driver instance
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*
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* @return N/A
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*/
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static void gpio_k64_port_isr(void *dev)
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{
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struct device *port = (struct device *)dev;
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struct gpio_k64_data *data = port->driver_data;
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struct gpio_k64_config *config = port->config->config_info;
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mem_addr_t int_status_reg_addr;
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uint32_t enabled_int, int_status, pin;
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if (!data->callback_func) {
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return;
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}
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int_status_reg_addr = config->port_base_addr +
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CONFIG_PORT_K64_INT_STATUS_OFFSET;
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int_status = sys_read32(int_status_reg_addr);
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if (data->port_callback_enable) {
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data->callback_func(port, int_status);
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} else if (data->pin_callback_enables) {
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/* perform callback for each callback-enabled pin with
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* an interrupt
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*/
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enabled_int = int_status & data->pin_callback_enables;
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while ((pin = find_lsb_set(enabled_int))) {
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pin--; /* normalize the pin number */
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data->callback_func(port, BIT(pin));
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/* clear the interrupt status */
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enabled_int &= ~BIT(pin);
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}
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}
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/* clear the port interrupts */
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sys_write32(0xFFFFFFFF, int_status_reg_addr);
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}
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static struct gpio_driver_api gpio_k64_drv_api_funcs = {
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.config = gpio_k64_config,
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.write = gpio_k64_write,
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.read = gpio_k64_read,
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.set_callback = gpio_k64_set_callback,
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.enable_callback = gpio_k64_enable_callback,
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.disable_callback = gpio_k64_disable_callback,
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};
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/**
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* @brief Initialization function of Freescale K64-based GPIO port
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*
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* @param dev Device structure pointer
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* @return 0 if successful, failed otherwise.
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*/
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int gpio_k64_init(struct device *dev)
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{
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dev->driver_api = &gpio_k64_drv_api_funcs;
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return 0;
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}
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/* Initialization for Port A */
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#ifdef CONFIG_GPIO_K64_A
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static int gpio_k64_A_init(struct device *dev);
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static struct gpio_k64_config gpio_k64_A_cfg = {
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.gpio_base_addr = GPIO_K64_A_BASE_ADDR,
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.port_base_addr = PORT_K64_A_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_A;
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DEVICE_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init,
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&gpio_data_A, &gpio_k64_A_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static int gpio_k64_A_init(struct device *dev)
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{
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IRQ_CONNECT(GPIO_K64_A_IRQ, CONFIG_GPIO_K64_PORTA_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0);
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irq_enable(GPIO_K64_A_IRQ);
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return gpio_k64_init(dev);
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}
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#endif /* CONFIG_GPIO_K64_A */
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/* Initialization for Port B */
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#ifdef CONFIG_GPIO_K64_B
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static int gpio_k64_B_init(struct device *dev);
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static struct gpio_k64_config gpio_k64_B_cfg = {
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.gpio_base_addr = GPIO_K64_B_BASE_ADDR,
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.port_base_addr = PORT_K64_B_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_B;
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DEVICE_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init,
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&gpio_data_B, &gpio_k64_B_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static int gpio_k64_B_init(struct device *dev)
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{
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IRQ_CONNECT(GPIO_K64_B_IRQ, CONFIG_GPIO_K64_PORTB_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0);
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irq_enable(GPIO_K64_B_IRQ);
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return gpio_k64_init(dev);
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}
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#endif /* CONFIG_GPIO_K64_B */
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/* Initialization for Port C */
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#ifdef CONFIG_GPIO_K64_C
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static int gpio_k64_C_init(struct device *dev);
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static struct gpio_k64_config gpio_k64_C_cfg = {
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.gpio_base_addr = GPIO_K64_C_BASE_ADDR,
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.port_base_addr = PORT_K64_C_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_C;
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DEVICE_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init,
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&gpio_data_C, &gpio_k64_C_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static int gpio_k64_C_init(struct device *dev)
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{
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IRQ_CONNECT(GPIO_K64_C_IRQ, CONFIG_GPIO_K64_PORTC_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0);
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irq_enable(GPIO_K64_C_IRQ);
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return gpio_k64_init(dev);
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}
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#endif /* CONFIG_GPIO_K64_C */
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/* Initialization for Port D */
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#ifdef CONFIG_GPIO_K64_D
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static int gpio_k64_D_init(struct device *dev);
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static struct gpio_k64_config gpio_k64_D_cfg = {
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.gpio_base_addr = GPIO_K64_D_BASE_ADDR,
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.port_base_addr = PORT_K64_D_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_D;
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DEVICE_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init,
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&gpio_data_D, &gpio_k64_D_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static int gpio_k64_D_init(struct device *dev)
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{
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IRQ_CONNECT(GPIO_K64_D_IRQ, CONFIG_GPIO_K64_PORTD_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0);
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irq_enable(GPIO_K64_D_IRQ);
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return gpio_k64_init(dev);
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}
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#endif /* CONFIG_GPIO_K64_D */
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/* Initialization for Port E */
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#ifdef CONFIG_GPIO_K64_E
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static int gpio_k64_E_init(struct device *dev);
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static struct gpio_k64_config gpio_k64_E_cfg = {
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.gpio_base_addr = GPIO_K64_E_BASE_ADDR,
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.port_base_addr = PORT_K64_E_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_E;
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DEVICE_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init,
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&gpio_data_E, &gpio_k64_E_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static int gpio_k64_E_init(struct device *dev)
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{
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IRQ_CONNECT(GPIO_K64_E_IRQ, CONFIG_GPIO_K64_PORTE_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0);
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irq_enable(GPIO_K64_E_IRQ);
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return gpio_k64_init(dev);
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}
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#endif /* CONFIG_GPIO_K64_E */
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