9ae310b923
This SoC has an external XCACHE controller for CPU0 instruction and data bus. Add code to enable the data cache. Instruction cache is already enabled by SystemInit. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
477 lines
15 KiB
C
477 lines
15 KiB
C
/*
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* Copyright 2024-2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include <soc.h>
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#include <fsl_glikey.h>
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/*!< System oscillator settling time in us */
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#define SYSOSC_SETTLING_US 220U
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/*!< xtal frequency in Hz */
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#define XTAL_SYS_CLK_HZ 24000000U
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#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
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#define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon0))
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#define EN_NUM 4
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#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
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#define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon1))
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#define EN_NUM 2
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#endif
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#define EDMA_EN_OFFSET 0x420
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#define EDMA_EN_REG(instance, idx) ((uint32_t *)((uint32_t)(SYSCON_BASE) + \
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(EDMA_EN_OFFSET) + 0x10U * (instance) + 4U * (idx)))
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#define SET_UP_FLEXCOMM_CLOCK(x) \
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do { \
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CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x); \
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RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn); \
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CLOCK_EnableClock(kCLOCK_LPFlexComm##x); \
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} while (0)
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#ifdef CONFIG_SOC_MIMXRT798S_CM33_CPU0
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#define SET_UP_CTIMER_CLOCK(x) \
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do { \
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CLOCK_AttachClk(kFRO0_DIV1_to_CTIMER##x); \
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CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U); \
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} while (0)
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#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
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#define SET_UP_CTIMER_CLOCK(x) \
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do { \
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CLOCK_AttachClk(kFRO2_DIV1_to_CTIMER##x); \
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CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U); \
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} while (0)
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#endif
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const clock_main_pll_config_t g_mainPllConfig_clock_init = {
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.main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */
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.numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */
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.denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
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.main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */
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};
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const clock_audio_pll_config_t g_audioPllConfig_clock_init = {
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.audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */
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.numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */
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.denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
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.audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */
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.enableVcoOut = true};
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static void BOARD_InitAHBSC(void);
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#if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
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static void edma_enable_all_request(uint8_t instance);
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#endif
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void board_early_init_hook(void)
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{
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#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
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const clock_fro_config_t froAutotrimCfg = {
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.targetFreq = 300000000U,
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.range = 50U,
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.trim1DelayUs = 15U,
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.trim2DelayUs = 15U,
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.refDiv = 1U,
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.enableInt = 0U,
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.coarseTrimEn = true,
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};
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POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
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/* Power up OSC */
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POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
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/* Enable system OSC */
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CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
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/* Sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
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/* Make sure FRO1 is enabled. */
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POWER_DisablePD(kPDRUNCFG_PD_FRO1);
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/* Switch to FRO1 for safe configure. */
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CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE);
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CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN);
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CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U);
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CLOCK_AttachClk(kFRO1_DIV1_to_RAM);
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CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U);
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CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
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CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN);
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CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U);
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#if CONFIG_FLASH_MCUX_XSPI_XIP
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/* Change to common_base clock(Sourced by FRO1). */
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xspi_clock_safe_config();
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#endif
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/* Ungate all FRO clock. */
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POWER_DisablePD(kPDRUNCFG_GATE_FRO0);
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/* Use close loop mode. */
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CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn);
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/* Enable FRO0 MAX clock for all domains.*/
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CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable);
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CLOCK_InitMainPll(&g_mainPllConfig_clock_init);
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CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475 MHz */
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CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396 MHz */
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CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528 MHz */
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/* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500 MHz -need 2 div -> 250 MHz*/
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CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable);
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CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
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CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 237.5 MHz */
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CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U);
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CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */
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/* Configure Audio PLL clock source. */
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CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */
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CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */
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CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
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CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
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CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
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#if CONFIG_FLASH_MCUX_XSPI_XIP
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/* Call function xspi_setup_clock() to set user configured clock for XSPI. */
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xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
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#endif /* CONFIG_FLASH_MCUX_XSPI_XIP */
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#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
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/* Power up OSC in case it's not enabled. */
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POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
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/* Enable system OSC */
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CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
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/* Sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
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CLOCK_AttachClk(kFRO1_DIV3_to_SENSE_BASE);
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CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
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CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
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POWER_DisablePD(kPDRUNCFG_GATE_FRO2);
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CLOCK_EnableFroClkFreq(FRO2, 300000000U, kCLOCK_FroAllOutEn);
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CLOCK_EnableFro2ClkForDomain(kCLOCK_AllDomainEnable);
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CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE);
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CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
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CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
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#endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */
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BOARD_InitAHBSC();
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay)
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CLOCK_EnableClock(kCLOCK_Dma0);
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RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn);
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edma_enable_all_request(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay)
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CLOCK_EnableClock(kCLOCK_Dma1);
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RESET_ClearPeripheralReset(kDMA1_RST_SHIFT_RSTn);
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edma_enable_all_request(1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon), okay)
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RESET_ClearPeripheralReset(kIOPCTL0_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon1), okay)
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RESET_ClearPeripheralReset(kIOPCTL1_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon2), okay)
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RESET_ClearPeripheralReset(kIOPCTL2_RST_SHIFT_RSTn);
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CLOCK_EnableClock(kCLOCK_Iopctl2);
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#endif
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#ifdef CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
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CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
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CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay)
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SET_UP_FLEXCOMM_CLOCK(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
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SET_UP_FLEXCOMM_CLOCK(1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
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SET_UP_FLEXCOMM_CLOCK(2);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
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SET_UP_FLEXCOMM_CLOCK(3);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
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SET_UP_FLEXCOMM_CLOCK(4);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
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SET_UP_FLEXCOMM_CLOCK(5);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm6), okay)
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SET_UP_FLEXCOMM_CLOCK(6);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm7), okay)
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SET_UP_FLEXCOMM_CLOCK(7);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm8), okay)
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SET_UP_FLEXCOMM_CLOCK(8);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm9), okay)
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SET_UP_FLEXCOMM_CLOCK(9);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm10), okay)
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SET_UP_FLEXCOMM_CLOCK(10);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm11), okay)
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SET_UP_FLEXCOMM_CLOCK(11);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm12), okay)
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SET_UP_FLEXCOMM_CLOCK(12);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm13), okay)
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SET_UP_FLEXCOMM_CLOCK(13);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi14), okay)
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CLOCK_AttachClk(kFRO1_DIV1_to_LPSPI14);
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CLOCK_SetClkDiv(kCLOCK_DivLpspi14Clk, 3U);
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CLOCK_EnableClock(kCLOCK_LPSpi14);
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RESET_ClearPeripheralReset(kLPSPI14_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c15), okay)
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CLOCK_EnableClock(kCLOCK_LPI2c15);
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RESET_ClearPeripheralReset(kLPI2C15_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi16), okay)
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CLOCK_AttachClk(kFRO0_DIV1_to_LPSPI16);
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CLOCK_SetClkDiv(kCLOCK_DivLpspi16Clk, 1U);
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CLOCK_EnableClock(kCLOCK_LPSpi16);
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RESET_ClearPeripheralReset(kLPSPI16_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm17), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM17);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm17Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm18), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM18);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm18Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm19), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM19);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm19Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm20), okay)
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CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM20);
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CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm20Clk, 4U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio), okay)
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CLOCK_AttachClk(kFRO0_DIV1_to_FLEXIO);
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CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1U);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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CLOCK_EnableClock(kCLOCK_Gpio0);
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RESET_ClearPeripheralReset(kGPIO0_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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CLOCK_EnableClock(kCLOCK_Gpio1);
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RESET_ClearPeripheralReset(kGPIO1_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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CLOCK_EnableClock(kCLOCK_Gpio2);
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RESET_ClearPeripheralReset(kGPIO2_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
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CLOCK_EnableClock(kCLOCK_Gpio3);
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RESET_ClearPeripheralReset(kGPIO3_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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CLOCK_EnableClock(kCLOCK_Gpio4);
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RESET_ClearPeripheralReset(kGPIO4_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
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CLOCK_EnableClock(kCLOCK_Gpio5);
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RESET_ClearPeripheralReset(kGPIO5_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
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CLOCK_EnableClock(kCLOCK_Gpio6);
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RESET_ClearPeripheralReset(kGPIO6_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
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CLOCK_EnableClock(kCLOCK_Gpio7);
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RESET_ClearPeripheralReset(kGPIO7_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay)
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CLOCK_EnableClock(kCLOCK_Gpio8);
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RESET_ClearPeripheralReset(kGPIO8_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay)
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CLOCK_EnableClock(kCLOCK_Gpio9);
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RESET_ClearPeripheralReset(kGPIO9_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio10), okay)
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CLOCK_EnableClock(kCLOCK_Gpio10);
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RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
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SET_UP_CTIMER_CLOCK(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
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SET_UP_CTIMER_CLOCK(1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
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SET_UP_CTIMER_CLOCK(2);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
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SET_UP_CTIMER_CLOCK(3);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
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SET_UP_CTIMER_CLOCK(4);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer5), okay)
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SET_UP_CTIMER_CLOCK(5);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer6), okay)
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SET_UP_CTIMER_CLOCK(6);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer7), okay)
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SET_UP_CTIMER_CLOCK(7);
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#endif
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}
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static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
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{
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(void)GLIKEY_SyncReset(base);
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(void)GLIKEY_StartEnable(base, idx);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3);
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(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN);
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}
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static void GlikeyClearConfig(GLIKEY_Type *base)
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{
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|
(void)GLIKEY_SyncReset(base);
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}
|
|
|
|
/* Disable the secure check for AHBSC and enable periperhals/sram access for masters */
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|
static void BOARD_InitAHBSC(void)
|
|
{
|
|
#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
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|
GlikeyWriteEnable(GLIKEY0, 1U);
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|
AHBSC0->MISC_CTRL_DP_REG = 0x000086aa;
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|
/* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */
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AHBSC0->MISC_CTRL_REG = 0x000086aa;
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|
|
|
GlikeyWriteEnable(GLIKEY0, 7U);
|
|
/* Enable arbiter0 accessing SRAM */
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|
AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
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|
AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
#endif
|
|
|
|
GlikeyWriteEnable(GLIKEY1, 1U);
|
|
AHBSC3->MISC_CTRL_DP_REG = 0x000086aa;
|
|
/* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/
|
|
AHBSC3->MISC_CTRL_REG = 0x000086aa;
|
|
|
|
GlikeyWriteEnable(GLIKEY1, 9U);
|
|
/* Enable arbiter1 accessing SRAM */
|
|
AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
|
|
|
|
GlikeyWriteEnable(GLIKEY1, 8U);
|
|
/* Access enable for COMPUTE domain masters to common APB peripherals.*/
|
|
AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
|
AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
|
GlikeyWriteEnable(GLIKEY1, 7U);
|
|
AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
|
AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
|
|
|
|
GlikeyWriteEnable(GLIKEY2, 1U);
|
|
/*Disable secure and secure privilege checking. */
|
|
AHBSC4->MISC_CTRL_DP_REG = 0x000086aa;
|
|
AHBSC4->MISC_CTRL_REG = 0x000086aa;
|
|
|
|
#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
|
|
GlikeyClearConfig(GLIKEY0);
|
|
#endif
|
|
GlikeyClearConfig(GLIKEY1);
|
|
GlikeyClearConfig(GLIKEY2);
|
|
}
|
|
|
|
#if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
|
|
static void edma_enable_all_request(uint8_t instance)
|
|
{
|
|
uint32_t *reg;
|
|
|
|
for (uint8_t idx = 0; idx < EN_NUM; idx++) {
|
|
reg = EDMA_EN_REG(instance, idx);
|
|
*reg |= 0xFFFFFFFF;
|
|
}
|
|
}
|
|
#endif
|