Some RISC-V SoCs implement a mechanism for hardware supported stacking / unstacking of registers during ISR / exceptions. What happens is that on ISR / exception entry part of the context is automatically saved by the hardware on the stack without software intervention, and the same part of the context is restored by the hardware usually on mret. This is currently not yet supported by Zephyr, where the full context must be saved by software in the full fledged ESF. This patcheset is trying to address exactly this case. At least three things are needed to support in a general fashion this problem: (1) a way to store in software only the part of the ESF not already stacked by hardware, (2) a way to restore in software only the part of the context that is not going to be restored by hardware and (3) a way to define a custom ESF. Point (3) is important because the full ESF frame is now composed by a custom part depending on the hardware (that can choose which register to stack / unstack and the order they are saved onto the stack) and a part defined in software for the remaining part of the context. In this patch a new CONFIG_RISCV_SOC_HAS_ISR_STACKING is introduced that enables the code path supporting the three points by the mean of three macros that must be implemented by the user in a soc_stacking.h file: SOC_ISR_SW_STACKING, SOC_ISR_SW_UNSTACKING and SOC_ISR_STACKING_ESF (refer to the symbol help for more details). This is an example of soc_isr_stacking.h for an hardware that doesn't do any hardware stacking / unstacking but everything is managed in software: #ifndef __SOC_ISR_STACKING #define __SOC_ISR_STACKING #if !defined(_ASMLANGUAGE) #define SOC_ISR_STACKING_ESF_DECLARE \ struct __esf { \ unsigned long ra; \ unsigned long t0; \ unsigned long t1; \ unsigned long t2; \ unsigned long t3; \ unsigned long t4; \ unsigned long t5; \ unsigned long t6; \ unsigned long a0; \ unsigned long a1; \ unsigned long a2; \ unsigned long a3; \ unsigned long a4; \ unsigned long a5; \ unsigned long a6; \ unsigned long a7; \ unsigned long mepc; \ unsigned long mstatus; \ unsigned long s0; \ } __aligned(16) #else #define SOC_ISR_SW_STACKING \ addi sp, sp, -__z_arch_esf_t_SIZEOF; \ DO_CALLER_SAVED(sr); #define SOC_ISR_SW_UNSTACKING \ DO_CALLER_SAVED(lr); #endif /* _ASMLANGUAGE */ #endif /* __SOC_ISR_STACKING */ Signed-off-by: Carlo Caione <ccaione@baylibre.com> |
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arc | ||
arm | ||
arm64 | ||
common | ||
mips | ||
nios2 | ||
posix | ||
riscv | ||
sparc | ||
x86 | ||
xtensa | ||
CMakeLists.txt | ||
Kconfig |