Kai Vehmanen e0bcf9f959 xtensa: cavs: add uncached ram sections to cavs25 linker script ... Align cavs25 with cavs15/18 and add memory segment for uncached mapping of the SRAM to linker script. Assign sections to uncached and cached segments as done in cavs15/18. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>		2021-06-14 21:48:44 -04:00
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esp32	linker: esp32: fix empty iterable symbols	2021-05-13 22:03:39 -04:00
intel_adsp	xtensa: cavs: add uncached ram sections to cavs25 linker script	2021-06-14 21:48:44 -04:00
intel_s1000	soc: xtensa: linker: Update linker scripts for C++ build	2021-05-28 09:32:44 -05:00
sample_controller	cmake: c++ exceptions linking support	2021-05-27 07:43:28 -05:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00