97ada8bc04
This is trick (mapping RAM twice so you can use alternate Region Protection Option addresses to control cacheability) is something any Xtensa hardware designer might productively choose to do. And as it works really well, we should encourage that by making this a generic architecture feature for Zephyr. Now everything works by setting two kconfig values at the soc level defining the cached and uncached regions. As long as these are correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that provides much smaller initialization code (in C!) than the HAL assembly macros. The conversion routines have been generalized to support conversion between any two regions. Note that full KERNEL_COHERENCE still requires support from the platform linker script, that can't be made generic given the way Zephyr does linkage. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INTEL_ADSP_CPU_INIT_H
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#define __INTEL_ADSP_CPU_INIT_H
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#include <arch/xtensa/cache.h>
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#include <xtensa/config/core-isa.h>
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#define CxL1CCAP (*(volatile uint32_t *)0x9F080080)
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#define CxL1CCFG (*(volatile uint32_t *)0x9F080084)
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#define CxL1PCFG (*(volatile uint32_t *)0x9F080088)
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/* "Data/Instruction Cache Memory Way Count" fields */
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#define CxL1CCAP_DCMWC ((CxL1CCAP >> 16) & 7)
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#define CxL1CCAP_ICMWC ((CxL1CCAP >> 20) & 7)
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/* Low-level CPU initialization. Call this immediately after entering
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* C code to initialize the cache, protection and synchronization
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* features.
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*/
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static ALWAYS_INLINE void cpu_early_init(void)
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{
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uint32_t reg;
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if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25)) {
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/* First, on cAVS 2.5 we need to power the cache SRAM banks
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* on! Write a bit for each cache way in the bottom half of
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* the L1CCFG register and poll the top half for them to turn
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* on.
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*/
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uint32_t dmask = BIT(CxL1CCAP_DCMWC) - 1;
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uint32_t imask = BIT(CxL1CCAP_ICMWC) - 1;
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uint32_t waymask = (imask << 8) | dmask;
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CxL1CCFG = waymask;
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while (((CxL1CCFG >> 16) & waymask) != waymask) {
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}
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/* Prefetcher also power gates, same interface */
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CxL1PCFG = 1;
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while ((CxL1PCFG & 0x10000) == 0) {
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}
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}
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/* Now set up the Xtensa CPU to enable the cache logic. The
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* details of the fields are somewhat complicated, but per the
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* ISA ref: "Turning on caches at power-up usually consists of
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* writing a constant with bits[31:8] all 1’s to MEMCTL.".
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* Also set bit 0 to enable the LOOP extension instruction
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* fetch buffer.
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*/
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#if XCHAL_USE_MEMCTL
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reg = 0xffffff01;
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__asm__ volatile("wsr %0, MEMCTL; rsync" :: "r"(reg));
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#endif
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/* Likewise enable prefetching. Sadly these values are not
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* architecturally defined by Xtensa (they're just documented
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* as priority hints), so this constant is just copied from
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* SOF for now. If we care about prefetch priority tuning
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* we're supposed to ask Cadence I guess.
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*/
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reg = IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25) ? 0x1038 : 0;
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__asm__ volatile("wsr %0, PREFCTL; rsync" :: "r"(reg));
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/* Finally we need to enable the cache in the Region
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* Protection Option "TLB" entries. The hardware defaults
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* have this set to RW/uncached everywhere.
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*/
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ARCH_XTENSA_SET_RPO_TLB();
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/* Initialize ATOMCTL: Hardware defaults for S32C1I use
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* "internal" operations, meaning they are atomic only WRT the
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* local CPU! We need external transactions on the shared
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* bus.
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*/
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reg = 0x15;
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__asm__ volatile("wsr %0, ATOMCTL" :: "r"(reg));
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/* Initialize interrupts to "disabled" */
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reg = 0;
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__asm__ volatile("wsr %0, INTENABLE" :: "r"(reg));
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/* Finally VECBASE. Note that on core 0 startup, we're still
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* running in IMR and the vectors at this address won't be
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* copied into HP-SRAM until later. That's OK, as interrupts
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* are still disabled at this stage and will remain so
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* consistently until Zephyr switches into the main thread.
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*/
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reg = XCHAL_VECBASE_RESET_PADDR_SRAM;
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__asm__ volatile("wsr %0, VECBASE" :: "r"(reg));
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}
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#endif /* __INTEL_ADSP_CPU_INIT_H */
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