This code component is used to add Zephyr support on iMX7 processors, exclusively on Cortex M4 core, and to speed up the development process it was decided to have it based on NXP FreeRTOS BSP implementation. The source code was imported from the following folders: FreeRTOS_BSP_1.0.1_iMX7D/platform/drivers FreeRTOS_BSP_1.0.1_iMX7D/platform/devices This source code depends on headers and sources from zephyr: ext/hal/cmsis Origin: iMX7D NXP FreeRTOS BSP Peripheral Driver License: BSD 3-Clause URL: https://www.nxp.com/webapp/Download?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=license commit: no commit hash Purpose: The peripheral driver wraps the H/W for i.MX7 M4 core Maintained-by: External Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mu_imx.h"
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_TrySendMsg
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* Description : Try to send message to the other core.
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*
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*END**************************************************************************/
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mu_status_t MU_TrySendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg)
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{
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assert(regIndex < MU_TR_COUNT);
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// TX register is empty.
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if(MU_IsTxEmpty(base, regIndex))
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{
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base->TR[regIndex] = msg;
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return kStatus_MU_Success;
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}
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return kStatus_MU_TxNotEmpty;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_SendMsg
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* Description : Wait and send message to the other core.
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*
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*END**************************************************************************/
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void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg)
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{
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assert(regIndex < MU_TR_COUNT);
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uint32_t mask = MU_SR_TE0_MASK >> regIndex;
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// Wait TX register to be empty.
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while (!(base->SR & mask)) { }
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base->TR[regIndex] = msg;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_TryReceiveMsg
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* Description : Try to receive message from the other core.
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*
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*END**************************************************************************/
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mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg)
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{
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assert(regIndex < MU_RR_COUNT);
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// RX register is full.
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if(MU_IsRxFull(base, regIndex))
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{
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*msg = base->RR[regIndex];
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return kStatus_MU_Success;
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}
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return kStatus_MU_RxNotFull;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_ReceiveMsg
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* Description : Wait to receive message from the other core.
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*
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*END**************************************************************************/
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void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg)
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{
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assert(regIndex < MU_TR_COUNT);
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uint32_t mask = MU_SR_RF0_MASK >> regIndex;
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// Wait RX register to be full.
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while (!(base->SR & mask)) { }
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*msg = base->RR[regIndex];
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_TriggerGeneralInt
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* Description : Trigger general purpose interrupt to the other core.
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*
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*END**************************************************************************/
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mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index)
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{
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// Previous interrupt has been accepted.
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if (MU_IsGeneralIntAccepted(base, index))
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{
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// All interrupts have been accepted, trigger now.
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base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn
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| (MU_CR_GIR0_MASK>>index); // Set GIRn
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return kStatus_MU_Success;
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}
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return kStatus_MU_IntPending;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_TrySetFlags
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* Description : Try to set some bits of the 3-bit flag.
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*
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*END**************************************************************************/
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mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags)
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{
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if(MU_IsFlagPending(base))
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{
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return kStatus_MU_FlagPending;
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}
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base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags;
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return kStatus_MU_Success;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : MU_SetFlags
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* Description : Block to set some bits of the 3-bit flag.
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*
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*END**************************************************************************/
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void MU_SetFlags(MU_Type * base, uint32_t flags)
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{
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while (MU_IsFlagPending(base)) { }
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base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags;
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}
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/*******************************************************************************
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* EOF
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******************************************************************************/
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