3afc2b6c61
This code component is used to add Zephyr support on iMX7 processors,
exclusively on Cortex M4 core, and to speed up the development process
it was decided to have it based on NXP FreeRTOS BSP implementation.
The source code was imported from the following folders:
FreeRTOS_BSP_1.0.1_iMX7D/platform/drivers
FreeRTOS_BSP_1.0.1_iMX7D/platform/devices
This source code depends on headers and sources from zephyr:
ext/hal/cmsis
Origin: iMX7D NXP FreeRTOS BSP Peripheral Driver
License: BSD 3-Clause
URL: https://www.nxp.com/webapp/Download?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=license
commit: no commit hash
Purpose: The peripheral driver wraps the H/W for i.MX7 M4 core
Maintained-by: External
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
803 lines
30 KiB
C
803 lines
30 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "adc_imx7d.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*******************************************************************************
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* ADC Module Initialization and Configuration functions.
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_Init
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* Description : Initialize ADC to reset state and initialize with initialize
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* structure.
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*
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*END**************************************************************************/
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void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig)
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{
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assert(initConfig);
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/* Reset ADC register to its default value. */
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ADC_Deinit(base);
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/* Set ADC Module Sample Rate */
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ADC_SetSampleRate(base, initConfig->sampleRate);
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/* Enable ADC Build-in voltage level shifter */
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if (initConfig->levelShifterEnable)
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ADC_LevelShifterEnable(base);
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else
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ADC_LevelShifterDisable(base);
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/* Wait until ADC module power-up completely. */
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while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK));
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_Deinit
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* Description : This function reset ADC module register content to its
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* default value.
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*
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*END**************************************************************************/
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void ADC_Deinit(ADC_Type* base)
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{
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/* Stop all continues conversions */
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ADC_SetConvertCmd(base, adcLogicChA, false);
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ADC_SetConvertCmd(base, adcLogicChB, false);
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ADC_SetConvertCmd(base, adcLogicChC, false);
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ADC_SetConvertCmd(base, adcLogicChD, false);
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/* Reset ADC Module Register content to default value */
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ADC_CH_A_CFG1_REG(base) = 0x0;
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ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
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ADC_CH_B_CFG1_REG(base) = 0x0;
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ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
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ADC_CH_C_CFG1_REG(base) = 0x0;
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ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
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ADC_CH_D_CFG1_REG(base) = 0x0;
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ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
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ADC_CH_SW_CFG_REG(base) = 0x0;
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ADC_TIMER_UNIT_REG(base) = 0x0;
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ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF);
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ADC_INT_SIG_EN_REG(base) = 0x0;
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ADC_INT_EN_REG(base) = 0x0;
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ADC_INT_STATUS_REG(base) = 0x0;
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ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetSampleRate
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* Description : This function is used to set ADC module sample rate.
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*
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*END**************************************************************************/
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void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate)
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{
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uint8_t preDiv;
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uint8_t coreTimerUnit;
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assert((sampleRate <= 1000000) && (sampleRate >= 1563));
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for (preDiv = 0 ; preDiv < 6; preDiv++)
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{
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uint32_t divider = 24000000 >> (2 + preDiv);
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divider /= sampleRate * 6;
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if(divider <= 32)
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{
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coreTimerUnit = divider - 1;
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break;
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}
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}
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if (0x6 == preDiv)
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{
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preDiv = 0x5;
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coreTimerUnit = 0x1F;
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}
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ADC_TIMER_UNIT_REG(base) = 0x0;
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ADC_TIMER_UNIT_REG(base) = ADC_TIMER_UNIT_PRE_DIV(preDiv) | ADC_TIMER_UNIT_CORE_TIMER_UNIT(coreTimerUnit);
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}
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/*******************************************************************************
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* ADC Low power control functions.
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetClockDownCmd
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* Description : This function is used to stop all digital part power.
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*
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*END**************************************************************************/
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void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown)
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{
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if (clockDown)
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ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_CLK_DOWN_MASK;
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else
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ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_CLK_DOWN_MASK;
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetPowerDownCmd
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* Description : This function is used to power down ADC analogue core.
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* Before entering into stop-mode, power down ADC analogue
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* core first.
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*
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*END**************************************************************************/
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void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown)
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{
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if (powerDown)
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{
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ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_PD_MASK;
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/* Wait until power down action finish. */
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while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK));
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}
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else
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{
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ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_PD_MASK;
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}
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}
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/*******************************************************************************
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* ADC Convert Channel Initialization and Configuration functions.
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_LogicChInit
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* Description : Initialize ADC Logic channel with initialization structure.
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*
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*END**************************************************************************/
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void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig)
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{
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assert(chInitConfig);
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/* Select input channel */
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ADC_SelectInputCh(base, logicCh, chInitConfig->inputChannel);
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/* Set Continuous Convert Rate. */
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if (chInitConfig->coutinuousEnable)
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ADC_SetConvertRate(base, logicCh, chInitConfig->convertRate);
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/* Set Hardware average Number. */
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if (chInitConfig->averageEnable)
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{
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ADC_SetAverageNum(base, logicCh, chInitConfig->averageNumber);
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ADC_SetAverageCmd(base, logicCh, true);
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_LogicChDeinit
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* Description : Reset target ADC logic channel registers to default value.
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*
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*END**************************************************************************/
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void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh)
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{
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assert(logicCh <= adcLogicChSW);
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) = 0x0;
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ADC_CH_A_CFG2_REG(base) = 0x8000;
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) = 0x0;
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ADC_CH_B_CFG2_REG(base) = 0x8000;
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) = 0x0;
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ADC_CH_C_CFG2_REG(base) = 0x8000;
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) = 0x0;
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ADC_CH_D_CFG2_REG(base) = 0x8000;
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break;
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case adcLogicChSW:
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ADC_CH_SW_CFG_REG(base) = 0x0;
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break;
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default:
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break;
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SelectInputCh
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* Description : Select input channel for target logic channel.
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*
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*END**************************************************************************/
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void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh)
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{
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assert(logicCh <= adcLogicChSW);
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \
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ADC_CH_A_CFG1_CHA_SEL(inputCh);
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SEL_MASK) | \
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ADC_CH_B_CFG1_CHB_SEL(inputCh);
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SEL_MASK) | \
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ADC_CH_C_CFG1_CHC_SEL(inputCh);
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SEL_MASK) | \
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ADC_CH_D_CFG1_CHD_SEL(inputCh);
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break;
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case adcLogicChSW:
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ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_SEL_MASK) | \
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ADC_CH_SW_CFG_CH_SW_SEL(inputCh);
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break;
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default:
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break;
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetConvertRate
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* Description : Set ADC conversion rate of target logic channel.
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*
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*END**************************************************************************/
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void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate)
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{
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assert(logicCh <= adcLogicChD);
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/* Calculate ADC module's current sample rate */
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uint32_t sampleRate = (4000000 >> (2 + (ADC_TIMER_UNIT_REG(base) >> ADC_TIMER_UNIT_PRE_DIV_SHIFT))) / \
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((ADC_TIMER_UNIT_REG(base) & ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) + 1);
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uint32_t convertDiv = sampleRate / convertRate;
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assert((sampleRate / convertRate) <= ADC_CH_A_CFG1_CHA_TIMER_MASK);
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \
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ADC_CH_A_CFG1_CHA_TIMER(convertDiv);
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_TIMER_MASK) | \
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ADC_CH_B_CFG1_CHB_TIMER(convertDiv);
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_TIMER_MASK) | \
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ADC_CH_C_CFG1_CHC_TIMER(convertDiv);
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_TIMER_MASK) | \
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ADC_CH_D_CFG1_CHD_TIMER(convertDiv);
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break;
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default:
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break;
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetAverageCmd
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* Description : Set work state of hardware average feature of target
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* logic channel.
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*
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*END**************************************************************************/
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void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable)
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{
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assert(logicCh <= adcLogicChSW);
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if (enable)
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{
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK;
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_AVG_EN_MASK;
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_AVG_EN_MASK;
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_AVG_EN_MASK;
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break;
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case adcLogicChSW:
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ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK;
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break;
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default:
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break;
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}
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}
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else
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{
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK;
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_AVG_EN_MASK;
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_AVG_EN_MASK;
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_AVG_EN_MASK;
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break;
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case adcLogicChSW:
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ADC_CH_SW_CFG_REG(base) &= ~ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK;
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break;
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default:
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break;
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}
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}
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetAverageNum
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* Description : Set hardware average number of target logic channel.
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*
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*END**************************************************************************/
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void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum)
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{
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assert(logicCh <= adcLogicChSW);
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assert(avgNum <= adcAvgNum32);
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) | \
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ADC_CH_A_CFG2_CHA_AVG_NUMBER(avgNum);
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break;
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case adcLogicChB:
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ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) | \
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ADC_CH_B_CFG2_CHB_AVG_NUMBER(avgNum);
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break;
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case adcLogicChC:
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ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) | \
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ADC_CH_C_CFG2_CHC_AVG_NUMBER(avgNum);
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break;
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case adcLogicChD:
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ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) | \
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ADC_CH_D_CFG2_CHD_AVG_NUMBER(avgNum);
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break;
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case adcLogicChSW:
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ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) | \
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ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(avgNum);
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break;
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default:
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break;
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}
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}
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/*******************************************************************************
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* ADC Conversion Control functions.
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : ADC_SetConvertCmd
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* Description : Set continuous convert work mode of target logic channel.
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*
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*END**************************************************************************/
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void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable)
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{
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assert(logicCh <= adcLogicChD);
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if (enable)
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{
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switch (logicCh)
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{
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case adcLogicChA:
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ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) |
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ADC_CH_A_CFG1_CHA_EN_MASK;
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break;
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case adcLogicChB:
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ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) |
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ADC_CH_B_CFG1_CHB_EN_MASK;
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break;
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case adcLogicChC:
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ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) |
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ADC_CH_C_CFG1_CHC_EN_MASK;
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break;
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case adcLogicChD:
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ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) |
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ADC_CH_D_CFG1_CHD_EN_MASK;
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break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK;
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK;
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK;
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_TriggerSingleConvert
|
|
* Description : Trigger single time convert on the target logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh)
|
|
{
|
|
assert(logicCh <= adcLogicChSW);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK;
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK;
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK;
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK;
|
|
break;
|
|
case adcLogicChSW:
|
|
ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_StopConvert
|
|
* Description : Stop current convert on the target logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_StopConvert(ADC_Type* base, uint8_t logicCh)
|
|
{
|
|
assert(logicCh <= adcLogicChSW);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK;
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK;
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK;
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK;
|
|
break;
|
|
case adcLogicChSW:
|
|
/* Wait until ADC conversion finish. */
|
|
while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_GetConvertResult
|
|
* Description : Get 12-bit length right aligned convert result.
|
|
*
|
|
*END**************************************************************************/
|
|
uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh)
|
|
{
|
|
assert(logicCh <= adcLogicChSW);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
return ADC_CHA_B_CNV_RSLT_REG(base) & ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK;
|
|
case adcLogicChB:
|
|
return ADC_CHA_B_CNV_RSLT_REG(base) >> ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT;
|
|
case adcLogicChC:
|
|
return ADC_CHC_D_CNV_RSLT_REG(base) & ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK;
|
|
case adcLogicChD:
|
|
return ADC_CHC_D_CNV_RSLT_REG(base) >> ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT;
|
|
case adcLogicChSW:
|
|
return ADC_CH_SW_CNV_RSLT_REG(base) & ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* ADC Comparer Control functions.
|
|
******************************************************************************/
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetCmpMode
|
|
* Description : Set the work mode of ADC module build-in comparer on target
|
|
* logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode)
|
|
{
|
|
assert(logicCh <= adcLogicChD);
|
|
assert(cmpMode <= adcCmpModeOutOffInterval);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) | \
|
|
ADC_CH_A_CFG2_CHA_CMP_MODE(cmpMode);
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) | \
|
|
ADC_CH_B_CFG2_CHB_CMP_MODE(cmpMode);
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) | \
|
|
ADC_CH_C_CFG2_CHC_CMP_MODE(cmpMode);
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) | \
|
|
ADC_CH_D_CFG2_CHD_CMP_MODE(cmpMode);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetCmpHighThres
|
|
* Description : Set ADC module build-in comparer high threshold on target
|
|
* logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold)
|
|
{
|
|
assert(logicCh <= adcLogicChD);
|
|
assert(threshold <= 0xFFF);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) | \
|
|
ADC_CH_A_CFG2_CHA_HIGH_THRES(threshold);
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) | \
|
|
ADC_CH_B_CFG2_CHB_HIGH_THRES(threshold);
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) | \
|
|
ADC_CH_C_CFG2_CHC_HIGH_THRES(threshold);
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) | \
|
|
ADC_CH_D_CFG2_CHD_HIGH_THRES(threshold);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetCmpLowThres
|
|
* Description : Set ADC module build-in comparer low threshold on target
|
|
* logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold)
|
|
{
|
|
assert(logicCh <= adcLogicChD);
|
|
assert(threshold <= 0xFFF);
|
|
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) | \
|
|
ADC_CH_A_CFG2_CHA_LOW_THRES(threshold);
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) | \
|
|
ADC_CH_B_CFG2_CHB_LOW_THRES(threshold);
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) | \
|
|
ADC_CH_B_CFG2_CHB_LOW_THRES(threshold);
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) | \
|
|
ADC_CH_D_CFG2_CHD_LOW_THRES(threshold);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetAutoDisableCmd
|
|
* Description : Set the working mode of ADC module auto disable feature on
|
|
* target logic channel.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable)
|
|
{
|
|
assert(logicCh <= adcLogicChD);
|
|
|
|
if (enable)
|
|
{
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG2_REG(base) |= ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG2_REG(base) |= ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG2_REG(base) |= ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG2_REG(base) |= ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (logicCh)
|
|
{
|
|
case adcLogicChA:
|
|
ADC_CH_A_CFG2_REG(base) &= ~ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChB:
|
|
ADC_CH_B_CFG2_REG(base) &= ~ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChC:
|
|
ADC_CH_C_CFG2_REG(base) &= ~ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
|
|
break;
|
|
case adcLogicChD:
|
|
ADC_CH_D_CFG2_REG(base) &= ~ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Interrupt and Flag control functions.
|
|
******************************************************************************/
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetIntCmd
|
|
* Description : Enables or disables ADC interrupt requests.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable)
|
|
{
|
|
if (enable)
|
|
ADC_INT_EN_REG(base) |= intSource;
|
|
else
|
|
ADC_INT_EN_REG(base) &= ~intSource;
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetIntSigCmd
|
|
* Description : Enables or disables ADC interrupt flag when interrupt
|
|
* condition met.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable)
|
|
{
|
|
if (enable)
|
|
ADC_INT_SIG_EN_REG(base) |= intSignal;
|
|
else
|
|
ADC_INT_SIG_EN_REG(base) &= ~intSignal;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* DMA & FIFO control functions.
|
|
******************************************************************************/
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetDmaReset
|
|
* Description : Set the reset state of ADC internal DMA part.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetDmaReset(ADC_Type* base, bool active)
|
|
{
|
|
if (active)
|
|
ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_RST_MASK;
|
|
else
|
|
ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_RST_MASK;
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetDmaCmd
|
|
* Description : Set the work mode of ADC DMA part.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetDmaCmd(ADC_Type* base, bool enable)
|
|
{
|
|
if (enable)
|
|
ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_EN_MASK;
|
|
else
|
|
ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_EN_MASK;
|
|
}
|
|
|
|
/*FUNCTION**********************************************************************
|
|
*
|
|
* Function Name : ADC_SetDmaFifoCmd
|
|
* Description : Set the work mode of ADC DMA FIFO part.
|
|
*
|
|
*END**************************************************************************/
|
|
void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable)
|
|
{
|
|
if (enable)
|
|
ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_FIFO_EN_MASK;
|
|
else
|
|
ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_FIFO_EN_MASK;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* EOF
|
|
******************************************************************************/
|