8d76b7b083
GCC enables unaligned memory access for ARMv6 and above. Once unaligned memory access is allowed, there's no need for the unaligned memory access trap. The change prevents the situation when the compiler generates code that uses unaligned memory access, but the CPU generates an exception when this code runs. Change-Id: Id33f2264c631772e5c561e76fb579d8b7bc26e1e Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
360 lines
8 KiB
C
360 lines
8 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Common fault handler for ARM Cortex-M
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*
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* Common fault handler for ARM Cortex-M processors.
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*/
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#include <toolchain.h>
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#include <sections.h>
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#include <nanokernel.h>
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#include <nano_private.h>
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#ifdef CONFIG_PRINTK
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#include <misc/printk.h>
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#define PR_EXC(...) printk(__VA_ARGS__)
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#else
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#define PR_EXC(...)
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#endif /* CONFIG_PRINTK */
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#if (CONFIG_FAULT_DUMP > 0)
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#define FAULT_DUMP(esf, fault) _FaultDump(esf, fault)
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#else
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#define FAULT_DUMP(esf, fault) \
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do { \
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(void) esf; \
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(void) fault; \
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} while ((0))
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#endif
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#if (CONFIG_FAULT_DUMP == 1)
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/**
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*
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* @brief Dump information regarding fault (FAULT_DUMP == 1)
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*
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* Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 1
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* (short form).
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*
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* eg. (precise bus error escalated to hard fault):
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*
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* Fault! EXC #3, Thread: 0x200000dc, instr: 0x000011d3
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* HARD FAULT: Escalation (see below)!
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* MMFSR: 0x00000000, BFSR: 0x00000082, UFSR: 0x00000000
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* BFAR: 0xff001234
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*
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* @return N/A
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*/
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void _FaultDump(const NANO_ESF *esf, int fault)
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{
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int escalation = 0;
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PR_EXC("Fault! EXC #%d, Thread: %x, instr @ %x\n",
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fault,
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sys_thread_self_get(),
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esf->pc);
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if (3 == fault) { /* hard fault */
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escalation = _ScbHardFaultIsForced();
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PR_EXC("HARD FAULT: %s\n",
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escalation ? "Escalation (see below)!"
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: "Bus fault on vector table read\n");
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}
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PR_EXC("MMFSR: %x, BFSR: %x, UFSR: %x\n",
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__scs.scb.cfsr.byte.mmfsr.val,
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__scs.scb.cfsr.byte.bfsr.val,
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__scs.scb.cfsr.byte.ufsr.val);
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if (_ScbMemFaultIsMmfarValid()) {
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PR_EXC("MMFAR: %x\n", _ScbMemFaultAddrGet());
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if (escalation) {
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_ScbMemFaultMmfarReset();
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}
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}
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if (_ScbBusFaultIsBfarValid()) {
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PR_EXC("BFAR: %x\n", _ScbBusFaultAddrGet());
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if (escalation) {
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_ScbBusFaultBfarReset();
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}
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}
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/* clear USFR sticky bits */
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_ScbUsageFaultAllFaultsReset();
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}
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#endif
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#if (CONFIG_FAULT_DUMP == 2)
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/**
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*
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* @brief Dump thread information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _FaultThreadShow(const NANO_ESF *esf)
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{
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PR_EXC(" Executing thread ID (thread): 0x%x\n"
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" Faulting instruction address: 0x%x\n",
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sys_thread_self_get(),
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esf->pc);
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}
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/**
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*
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* @brief Dump MPU fault information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
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{
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PR_EXC("***** MPU FAULT *****\n");
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_FaultThreadShow(esf);
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if (_ScbMemFaultIsStacking()) {
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PR_EXC(" Stacking error\n");
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} else if (_ScbMemFaultIsUnstacking()) {
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PR_EXC(" Unstacking error\n");
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} else if (_ScbMemFaultIsDataAccessViolation()) {
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PR_EXC(" Data Access Violation\n");
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if (_ScbMemFaultIsMmfarValid()) {
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PR_EXC(" Address: 0x%x\n", _ScbMemFaultAddrGet());
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if (fromHardFault) {
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_ScbMemFaultMmfarReset();
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}
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}
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} else if (_ScbMemFaultIsInstrAccessViolation()) {
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PR_EXC(" Instruction Access Violation\n");
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}
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}
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/**
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*
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* @brief Dump bus fault information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _BusFault(const NANO_ESF *esf, int fromHardFault)
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{
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PR_EXC("***** BUS FAULT *****\n");
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_FaultThreadShow(esf);
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if (_ScbBusFaultIsStacking()) {
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PR_EXC(" Stacking error\n");
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} else if (_ScbBusFaultIsUnstacking()) {
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PR_EXC(" Unstacking error\n");
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} else if (_ScbBusFaultIsPrecise()) {
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PR_EXC(" Precise data bus error\n");
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if (_ScbBusFaultIsBfarValid()) {
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PR_EXC(" Address: 0x%x\n", _ScbBusFaultAddrGet());
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if (fromHardFault) {
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_ScbBusFaultBfarReset();
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}
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}
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/* it's possible to have both a precise and imprecise fault */
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if (_ScbBusFaultIsImprecise()) {
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PR_EXC(" Imprecise data bus error\n");
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}
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} else if (_ScbBusFaultIsImprecise()) {
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PR_EXC(" Imprecise data bus error\n");
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} else if (_ScbBusFaultIsInstrBusErr()) {
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PR_EXC(" Instruction bus error\n");
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}
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}
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/**
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*
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* @brief Dump usage fault information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _UsageFault(const NANO_ESF *esf)
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{
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PR_EXC("***** USAGE FAULT *****\n");
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_FaultThreadShow(esf);
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/* bits are sticky: they stack and must be reset */
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if (_ScbUsageFaultIsDivByZero()) {
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PR_EXC(" Division by zero\n");
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}
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if (_ScbUsageFaultIsUnaligned()) {
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PR_EXC(" Unaligned memory access\n");
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}
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if (_ScbUsageFaultIsNoCp()) {
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PR_EXC(" No coprocessor instructions\n");
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}
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if (_ScbUsageFaultIsInvalidPcLoad()) {
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PR_EXC(" Illegal load of EXC_RETURN into PC\n");
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}
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if (_ScbUsageFaultIsInvalidState()) {
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PR_EXC(" Illegal use of the EPSR\n");
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}
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if (_ScbUsageFaultIsUndefinedInstr()) {
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PR_EXC(" Attempt to execute undefined instruction\n");
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}
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_ScbUsageFaultAllFaultsReset();
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}
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/**
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*
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* @brief Dump hard fault information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _HardFault(const NANO_ESF *esf)
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{
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PR_EXC("***** HARD FAULT *****\n");
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if (_ScbHardFaultIsBusErrOnVectorRead()) {
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PR_EXC(" Bus fault on vector table read\n");
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} else if (_ScbHardFaultIsForced()) {
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PR_EXC(" Fault escalation (see below)\n");
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if (_ScbIsMemFault()) {
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_MpuFault(esf, 1);
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} else if (_ScbIsBusFault()) {
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_BusFault(esf, 1);
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} else if (_ScbIsUsageFault()) {
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_UsageFault(esf);
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}
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}
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}
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/**
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*
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* @brief Dump debug monitor exception information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _DebugMonitor(const NANO_ESF *esf)
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{
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PR_EXC("***** Debug monitor exception (not implemented) *****\n");
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}
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/**
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*
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* @brief Dump reserved exception information
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*
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* See _FaultDump() for example.
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*
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* @return N/A
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*/
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static void _ReservedException(const NANO_ESF *esf, int fault)
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{
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PR_EXC("***** %s %d) *****\n",
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fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ",
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fault - 16);
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}
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/**
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*
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* @brief Dump information regarding fault (FAULT_DUMP == 2)
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*
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* Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 2
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* (long form).
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*
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* eg. (precise bus error escalated to hard fault):
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*
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* Executing thread ID (thread): 0x200000dc
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* Faulting instruction address: 0x000011d3
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* ***** HARD FAULT *****
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* Fault escalation (see below)
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* ***** BUS FAULT *****
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* Precise data bus error
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* Address: 0xff001234
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*
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* @return N/A
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*/
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static void _FaultDump(const NANO_ESF *esf, int fault)
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{
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switch (fault) {
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case 3:
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_HardFault(esf);
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break;
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case 4:
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_MpuFault(esf, 0);
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break;
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case 5:
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_BusFault(esf, 0);
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break;
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case 6:
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_UsageFault(esf);
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break;
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case 12:
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_DebugMonitor(esf);
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break;
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default:
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_ReservedException(esf, fault);
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break;
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}
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}
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#endif /* FAULT_DUMP == 2 */
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/**
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*
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* @brief Fault handler
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*
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* This routine is called when fatal error conditions are detected by hardware
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* and is responsible only for reporting the error. Once reported, it then
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* invokes the user provided routine _SysFatalErrorHandler() which is
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* responsible for implementing the error handling policy.
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*
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* Since the ESF can be either on the MSP or PSP depending if an exception or
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* interrupt was already being handled, it is passed a pointer to both and has
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* to find out on which the ESP is present.
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*
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* @param esf ESF on the stack, either MSP or PSP depending at what processor
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* state the exception was taken.
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*
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* @return This function does not return.
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*/
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void _Fault(const NANO_ESF *esf)
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{
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int fault = _ScbActiveVectorGet();
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FAULT_DUMP(esf, fault);
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_SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
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}
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/**
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*
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* @brief Initialization of fault handling
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*
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* Turns on the desired hardware faults.
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*
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* @return N/A
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*/
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void _FaultInit(void)
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{
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_ScbDivByZeroFaultEnable();
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}
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