zephyr/arch/x86
Andy Ross 9098a45c84 kernel: New timeslicing implementation
Instead of checking every time we hit the low-level context switch
path to see if the new thread has a "partner" with which it needs to
share time, just run the slice timer always and reset it from the
scheduler at the points where it has already decided a switch needs to
happen.  In TICKLESS_KERNEL situations, we pay the cost of extra timer
interrupts at ~10Hz or whatever, which is low (note also that this
kind of regular wakeup architecture is required on SMP anyway so the
scheduler can "notice" threads scheduled by other CPUs).  Advantages:

1. Much simpler logic.  Significantly smaller code.  No variance or
   dependence on tickless modes or timer driver (beyond setting a
   simple timeout).

2. No arch-specific assembly integration with _Swap() needed

3. Better performance on many workloads, as the accounting now happens
   at most once per timer interrupt (~5 Hz) and true rescheduling and
   not on every unrelated context switch and interrupt return.

4. It's SMP-safe.  The previous scheme kept the slice ticks as a
   global variable, which was an unnoticed bug.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
..
core kernel: New timeslicing implementation 2018-10-16 15:03:10 -04:00
include kernel: Using the same paramenters names in a specific function 2018-09-28 07:58:19 +05:30
CMakeLists.txt x86: move soc/cpu to top-level under soc/ 2018-09-13 00:56:48 -04:00
defconfig Use SoC instead of platform. 2016-02-05 20:25:11 -05:00
Kconfig kconfig: move soc selection to ZEPHYR_BASE/soc/ 2018-09-13 00:56:48 -04:00