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zephyr/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
Fabrice DJIATSA 905e3032a0 boards: stm32n6570_dk: add irq-gpios property 
There was a missing irq-gpios property that cause
building failure on lvgl and display samples.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2025-06-10 12:09:25 +02:00

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/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/n6/stm32n657X0.dtsi>
#include <st/n6/stm32n657x0hxq-pinctrl.dtsi>
#include "zephyr/dt-bindings/display/panel.h"
#include <zephyr/dt-bindings/flash_controller/xspi.h>
#include <zephyr/dt-bindings/gpio/raspberrypi-csi-22pins-connector.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/video/video-interfaces.h>
#include "arduino_r3_connector.dtsi"
/ {
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &axisram2;
zephyr,canbus = &fdcan1;
zephyr,display = &ltdc;
zephyr,touch = &gt911;
spi-flash0 = &mx66uw1g45g;
};
aliases {
led0 = &green_led_1;
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&gt911>;
display = <&ltdc>;
invert-y;
};
psram: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(32)>;
zephyr,memory-region = "PSRAM";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
red_led_1: led_2 {
gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
csi_22pins_connector: connector_csi_22pins {
compatible = "raspberrypi,csi-22pins-connector";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <CSI_22PINS_IO0 0 &gpioc 8 0>,
<CSI_22PINS_IO1 0 &gpiod 2 0>;
};
};
&i2c2 {
status = "okay";
clocks = <&rcc STM32_CLOCK(APB1, 22)>,
<&rcc STM32_SRC_CKPER I2C2_SEL(1)>;
pinctrl-0 = <&i2c2_scl_pd14 &i2c2_sda_pd4>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
gt911: gt911@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpioq 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
};
};
&clk_hse {
hse-div2;
clock-frequency = <DT_FREQ_M(48)>;
status = "okay";
};
&clk_hsi {
hsi-div = <1>;
status = "okay";
};
&pll1 {
clocks = <&clk_hse>;
div-m = <3>;
mul-n = <150>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay";
};
&pll2 {
clocks = <&clk_hsi>;
div-m = <2>;
mul-n = <48>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay";
};
&pll3 {
clocks = <&clk_hse>;
div-m = <3>;
mul-n = <125>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay";
};
&pll4 {
clocks = <&clk_hsi>;
div-m = <4>;
mul-n = <75>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay";
};
&ic1 {
pll-src = <1>;
ic-div = <3>;
status = "okay";
};
&ic2 {
pll-src = <1>;
ic-div = <6>;
status = "okay";
};
&ic3 {
pll-src = <1>;
ic-div = <6>;
status = "okay";
};
&ic4 {
pll-src = <2>;
ic-div = <32>;
status = "okay";
};
&ic6 {
pll-src = <3>;
ic-div = <2>;
status = "okay";
};
&ic11 {
pll-src = <1>;
ic-div = <3>;
status = "okay";
};
&ic16 {
pll-src = <4>;
ic-div = <60>;
status = "okay";
};
&ic17 {
pll-src = <1>;
ic-div = <4>;
status = "okay";
};
&ic18 {
pll-src = <1>;
ic-div = <60>;
status = "okay";
};
&perck {
clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
status = "okay";
};
&cpusw {
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
clock-frequency = <DT_FREQ_M(800)>;
status = "okay";
};
&rcc {
/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
clocks = <&ic2>;
clock-frequency = <DT_FREQ_M(400)>;
ahb-prescaler = <2>;
timg-prescaler = <2>;
};
&adc1 {
clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
<&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */
pinctrl-names = "default";
vref-mv = <1800>;
status = "okay";
};
&fdcan1 {
clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
<&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
pinctrl-names = "default";
status = "okay";
};
csi_22pins_i2c: &i2c1 {
clocks = <&rcc STM32_CLOCK(APB1, 21)>,
<&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
pinctrl-0 = <&i2c1_scl_ph9 &i2c1_sda_pc1>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&i2c4 {
clocks = <&rcc STM32_CLOCK(APB4, 7)>,
<&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
pinctrl-0 = <&i2c4_scl_pe13 &i2c4_sda_pe14>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
};
&sdmmc2 {
status = "okay";
clocks = <&rcc STM32_CLOCK(AHB5, 7)>,
<&rcc STM32_SRC_IC4 SDMMC2_SEL(2)>;
pinctrl-0 = <&sdmmc2_d0_pc4 &sdmmc2_d1_pc5
&sdmmc2_d2_pc0 &sdmmc2_d3_pe4
&sdmmc2_ck_pc2 &sdmmc2_cmd_pc3>;
pinctrl-names = "default";
bus-width = <4>;
cd-gpios = <&gpion 12 GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>;
disk-name = "SD";
};
&spi5 {
clocks = <&rcc STM32_CLOCK(APB2, 20)>,
<&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
pinctrl-0 = <&spi5_nss_pa3 &spi5_sck_pe15 &spi5_miso_ph8 &spi5_mosi_pg2>;
pinctrl-names = "default";
status = "okay";
};
&usart1 {
clocks = <&rcc STM32_CLOCK(APB2, 4)>,
<&rcc STM32_SRC_CKPER USART1_SEL(1)>;
pinctrl-0 = <&usart1_tx_pe5 &usart1_rx_pe6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
clocks = <&rcc STM32_CLOCK(APB1, 17)>,
<&rcc STM32_SRC_CKPER USART2_SEL(1)>;
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pf6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_hs1 {
status = "okay";
};
&xspi1 {
pinctrl-0 = <&xspim_p1_ncs1_po0 &xspim_p1_dqs0_po2
&xspim_p1_dqs1_po3 &xspim_p1_clk_po4
&xspim_p1_io0_pp0 &xspim_p1_io1_pp1 &xspim_p1_io2_pp2
&xspim_p1_io3_pp3 &xspim_p1_io4_pp4 &xspim_p1_io5_pp5
&xspim_p1_io6_pp6 &xspim_p1_io7_pp7 &xspim_p1_io8_pp8
&xspim_p1_io9_pp9 &xspim_p1_io10_pp10 &xspim_p1_io11_pp11
&xspim_p1_io12_pp12 &xspim_p1_io13_pp13 &xspim_p1_io14_pp14
&xspim_p1_io15_pp15>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";
memc: aps256xxn_obr: memory@0 {
compatible = "st,stm32-xspi-psram";
reg = <0>;
size = <DT_SIZE_M(256)>; /* 256 Mbits */
max-frequency = <DT_FREQ_M(200)>;
fixed-latency;
io-x16-mode;
read-latency = <4>;
write-latency = <1>;
burst-length = <0>;
status = "okay";
};
};
&xspi2 {
pinctrl-0 = <&xspim_p2_ncs1_pn1 &xspim_p2_dqs0_pn0 &xspim_p2_clk_pn6
&xspim_p2_io0_pn2 &xspim_p2_io1_pn3 &xspim_p2_io2_pn4
&xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";
mx66uw1g45g: ospi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0>;
size = <DT_SIZE_M(1024)>; /* 1Gbits */
ospi-max-frequency = <DT_FREQ_M(200)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
four-byte-opcodes;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@7ff0000 {
label = "storage";
reg = <0x7ff0000 DT_SIZE_K(64)>;
};
};
};
};
&mac {
status = "okay";
pinctrl-0 = <&eth1_rgmii_gtx_clk_pf0
&eth1_rgmii_clk125_pf2
&eth1_rgmii_rx_clk_pf7
&eth1_rgmii_rxd2_pf8
&eth1_rgmii_rxd3_pf9
&eth1_rgmii_rx_ctl_pf10
&eth1_rgmii_tx_ctl_pf11
&eth1_rgmii_txd1_pf13
&eth1_rgmii_txd0_pf12
&eth1_rgmii_rxd0_pf14
&eth1_rgmii_rxd1_pf15
&eth1_rgmii_txd2_pg3
&eth1_rgmii_txd3_pg4
&eth1_phy_intn_pd3>;
pinctrl-names = "default";
phy-connection-type = "rgmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth1_mdio_pd12 &eth1_mdc_pd1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x0>;
};
};
&ltdc {
clocks = <&rcc STM32_CLOCK(APB5, 1)>,
<&rcc STM32_SRC_IC16 LTDC_SEL(2)>;
pinctrl-0 = <&ltdc_r0_pg0 &ltdc_r1_pd9 &ltdc_r2_pd15 &ltdc_r3_pb4
&ltdc_r4_ph4 &ltdc_r5_pa15 &ltdc_r6_pg11 &ltdc_r7_pd8
&ltdc_g0_pg12 &ltdc_g1_pg1 &ltdc_g2_pa1 &ltdc_g3_pa0
&ltdc_g4_pb15 &ltdc_g5_pb12 &ltdc_g6_pb11 &ltdc_g7_pg8
&ltdc_b0_pg15 &ltdc_b1_pa7 &ltdc_b2_pb2 &ltdc_b3_pg6
&ltdc_b4_ph3 &ltdc_b5_ph6 &ltdc_b6_pa8 &ltdc_b7_pa2
&ltdc_de_pg13 &ltdc_clk_pb13 &ltdc_hsync_pb14 &ltdc_vsync_pe11>;
pinctrl-names = "default";
disp-on-gpios = <&gpioq 3 GPIO_ACTIVE_HIGH>;
bl-ctrl-gpios = <&gpioq 6 GPIO_ACTIVE_HIGH>;
ext-sdram = <&psram>;
status = "okay";
width = <800>;
height = <480>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
display-timings {
compatible = "zephyr,panel-timing";
de-active = <0>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
hsync-len = <4>;
vsync-len = <4>;
hback-porch = <8>;
vback-porch = <8>;
hfront-porch = <8>;
vfront-porch = <8>;
};
def-back-color-red = <0xFF>;
def-back-color-green = <0xFF>;
def-back-color-blue = <0xFF>;
};
csi_22pins_interface: &dcmipp {
ports {
port@0 {
csi_22pins_ep_in: endpoint { };
};
port@1 {
csi_22pins_capture_port: endpoint@1 { };
};
};
};
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