8bed2d5e27
By default, after reset SWO signal is not connected to GPIO pin. This commit adds required initialization code to enable support for SWO logger. Not all SoC series support the feature. Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
124 lines
2.4 KiB
Text
124 lines
2.4 KiB
Text
#include <arm/armv7-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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aliases {
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usart-0 = &usart0;
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usart-1 = &usart1;
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};
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soc {
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flash-controller@400e0000 {
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compatible = "silabs,gecko-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x400e0000 0x78>;
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interrupts = <24 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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write-block-size = <4>;
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};
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};
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usart0: usart@40010000 { /* USART0 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010000 0x400>;
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interrupts = <11 0>, <12 0>;
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interrupt-names = "rx", "tx";
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status = "disabled";
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label = "USART_0";
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};
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usart1: usart@40010400 { /* USART1 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010400 0x400>;
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interrupts = <19 0>, <20 0>;
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interrupt-names = "rx", "tx";
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status = "disabled";
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label = "USART_1";
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};
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gpio: gpio@4000a400 {
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compatible = "silabs,efr32xg1-gpio";
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reg = <0x4000a400 0xc00>;
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interrupts = <9 2 17 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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label = "GPIO";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@4000a000 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000a000 0x30>;
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label = "GPIO_A";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiob: gpio@4000a030 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000a030 0x30>;
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label = "GPIO_B";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@4000a060 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000a060 0x30>;
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label = "GPIO_C";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiod: gpio@4000a090 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000a090 0x30>;
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label = "GPIO_D";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioe: gpio@4000a0c0 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000a0c0 0x30>;
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label = "GPIO_E";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiof: gpio@4000a0f0 {
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compatible = "silabs,efr32xg1-gpio-port";
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reg = <0x4000af0 0x30>;
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label = "GPIO_F";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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